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mirror of https://review.coreboot.org/flashrom.git synced 2025-04-27 15:12:36 +02:00
Brian Norris 54b053e6b2 udelay: Lower the sleep vs delay threshold
By default, we busy-loop (a.k.a., "delay") for most delay values, and
only allow sleeping for large delays. But busy-looping is expensive, as
it wastes CPU cycles.

In a simple program that runs a bunch of samples of [1] over 1000
samples, I find that for 0.1 s (100000 us):

 64x2 AMD CPU (CONFIG_HZ=250 / CONFIG_NO_HZ_FULL=y):
   min diff: 60 us
   max diff: 831 us
   mean diff: 135 us

 4+2 Mediatek MT8183 CPU (CONFIG_HZ=1000 / CONFIG_NO_HZ_IDLE=y /
                          sysctl kernel.timer_highres=1):
   min diff: 70 us
   max diff: 1556 us
   mean diff: 146 us

 4+2 Mediatek MT8183 CPU (CONFIG_HZ=1000 / CONFIG_NO_HZ_IDLE=y /
                          sysctl kernel.timer_highres=0):
   min diff: 94 us
   max diff: 7222 us
   mean diff: 1201 us

i.e., maximum 1.5% error, typically ~0.1% error with high resolution
timers. Max 7% error, typical 1% error with low resolution timers. The
error is always in the positive direction (i.e., sleep longer than the
requested delay, not shorter than the request).

This seems reasonable.

[1] Stripped / pseudocode:

  clock_gettime(CLOCK_MONOTONIC, before);
  nanosleep({ .tv_nsec = usecs * 1000 }, NULL);
  clock_gettime(CLOCK_MONOTONIC, after);
  diff = abs((after - before) / 1000 - usecs));

Change-Id: Ifd4821c66c5564f7c975c08769a6742f645e9be0
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/80808
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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flashrom README
===============

flashrom is a utility for detecting, reading, writing, verifying and erasing
flash chips. It is often used to flash BIOS/EFI/coreboot/firmware images
in-system using a supported mainboard, but it also supports flashing of network
cards (NICs), SATA controller cards, and other external devices which can
program flash chips.

It supports a wide range of flash chips (most commonly found in SOIC8, DIP8,
SOIC16, WSON8, PLCC32, DIP32, TSOP32, and TSOP40 packages), which use various
protocols such as LPC, FWH, parallel flash, or SPI.

Do not use flashrom on laptops (yet)! The embedded controller (EC) present in
many laptops might interact badly with any attempts to communicate with the
flash chip and may brick your laptop.

Please make a backup of your flash chip before writing to it.

Please see the flashrom(8) manpage :doc:`classic_cli_manpage`.


Building / installing / packaging
---------------------------------

flashrom supports building with **make** and **meson**.

TLDR, building with meson
"""""""""""""""""""""""""

::

    meson setup builddir
    meson compile -C builddir
    meson test -C builddir
    meson install -C builddir

For full detailed instructions, follow the information in
:doc:`dev_guide/building_from_source`

TLDR, building with make
""""""""""""""""""""""""

::

	make
	make install

For full detailed instructions, follow the information in
:doc:`dev_guide/building_with_make`

Contact
-------

The official flashrom website is:

  https://www.flashrom.org/

For available contact methods see :doc:`contact`
Description
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Readme 75 MiB
Languages
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Rust 5%
Shell 2%
Makefile 1.6%
Meson 1.2%