87134f538d
tree: Remove print_wiki.c
...
Old wiki website is retired and so is print_wiki.c
Change-Id: I9990add27f7fdddc23ddd1f33306566ce7548417
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Peter Marheine <pmarheine@chromium.org >
2024-08-22 01:22:27 +00:00
97922fba17
flashchips: add GD25LF512MF model
...
GD25LF512MF: 1.8V 512Mbit high performance, quad IO enabled.
Tested on ch347 with erase, write, read, and protection
Change-Id: I3d202f5afcc9c33a4040f8186dc6fef1878ba79a
Signed-off-by: Victor Lim <vlim@gigadevice.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83912
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2024-08-20 13:12:16 +00:00
8685230caa
flashchips: adding GD25LB512MF/GD25LR512MF
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GD25LB512MF: 1.8V 512Mbit shipped with Quad enabled.
https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20231213/DS-01012-GD25LB512MF-Rev1.0.pdf
GD25LR512MF: all GD25LB512MF features + RPMC feature
The datasheet is identical with GD25LB512MF for the NOR flash side.
Tested both models on ch347 with erase, read, write, and protection.
Change-Id: I6a0061a43af5966c93c95645b51a640c00f3d829
Signed-off-by: Victor Lim <vlim@gigadevice.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83899
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2024-08-17 08:06:19 +00:00
e4cb19a489
flashchips: add support for MX77U51250F chip
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Add initial support for Macronix MX77U51250F.
BUG=none
BRANCH=none
TEST= Tested read, write and probe on google/fatcat with internal
programmer.
Change-Id: I2c2e94f01dc63f60cf636bc6afe1f033e2a6f83c
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/82626
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: DZ <danielzhang@mxic.com.cn >
2024-08-17 08:05:54 +00:00
126de26b44
flashchips: add GD25LB512ME
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Added GD25LB512ME to Flashchips.C
added Sames as GD25LB512ME to GIGADEVICE_GD25LR512ME to flashchips.h
GD25LB512ME is 1.8V 512Mbit, Quad enabled when shipped.
https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230627/DS-00580-GD25LB512ME-Rev1.5.pdf
Tested on ch347 with erase, program, read, and protection.
Change-Id: I04103814f901478098c1a989f4239792b64073ec
Signed-off-by: Victor Lim <vlim@gigadevice.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2024-08-15 12:51:44 +00:00
9c3aed0269
flashrom.c: Rename {erase|write}_by_layout_new as the only one
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We used to have two code paths for erase and write, so we had
{erase|write}_by_layout in two variants: *_new and *_legacy.
Now that legacy is removed, *_new can be renamed without *_new
suffix.
Change-Id: Ib21bf29e1993c4fc0516e76fde2ad283eedb50d2
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aarya <aarya.chaumal@gmail.com >
Reviewed-by: Peter Marheine <pmarheine@chromium.org >
2024-08-15 02:27:52 +00:00
5ddd3b55fc
flashrom.c: Delete legacy erase and write logic
...
Current code path for erase and write has been enabled in the tree
since May 2023, which is more than 1 year ago (15 months ago),
and legacy path has been disabled since the same time.
Current logic has been officially released in v1.4.0 in July 2024.
Change-Id: I08fd686fecf6a5313eea2d66b368661c664f4800
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aarya <aarya.chaumal@gmail.com >
Reviewed-by: Peter Marheine <pmarheine@chromium.org >
2024-08-15 02:27:03 +00:00
213fdb0f9f
doc: Add doc describing release process
...
Change-Id: Id6aacf5ef3879a5e236759e7a4a6af3cf7cc0a00
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83762
Reviewed-by: Peter Marheine <pmarheine@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2024-08-12 12:16:14 +00:00
133b112d09
Remove the Makefile
...
As was described in the version 1.4 release notes, this deletes the
Makefile and supporting elements leaving Meson as the only supported
buildsystem.
Signed-off-by: Peter Marheine <pmarheine@chromium.org >
Change-Id: Ib3cf22cf636ef9b70527b734ffa34aead2a74edd
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2024-08-12 00:09:12 +00:00
03090fec0a
flashchips: add GD25LF256F
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added GD25LF256F on flashchips.c
added GIGADEVICE_GD25LF256F=0x6319 on flashchip.h
GD25LF256F is a higher performance 1.8V 256Mbit SPI flash
I have tested on CH347 with erase, program, read, protection.
Change-Id: I21a71606476e823faa38a7920aa2b10e25d68d26
Signed-off-by: Victor <vlim@gigadevice.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2024-08-09 12:59:12 +00:00
3d7094ad09
doc: Convert the doc for MSI JSPI1
...
The doc converted from
https://wiki.flashrom.org/MSI_JSPI1
Change-Id: Idd215a3a3a4d62629803a71d360755c43c1ab599
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: David Hendricks <david.hendricks@gmail.com >
2024-08-09 02:13:46 +00:00
fd97d5b2a4
doc: Fix the link to In-System programming doc
...
Change-Id: Ic82be2b926b0d3a9de7d4b030bbef31c1b3746fb
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Peter Marheine <pmarheine@chromium.org >
2024-08-08 00:14:39 +00:00
f1ddf46820
doc: Add overview doc for user_docs
...
This document is converted from Technology page on wiki
https://wiki.flashrom.org/Technology
Change-Id: I93107d6b5530c301dd90f7177758632d9d1810eb
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83584
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2024-08-03 08:52:13 +00:00
d99afdc026
doc: Add doc for buspirate programmer
...
Doc migrated from the wiki page:
https://wiki.flashrom.org/Bus_Pirate
Change-Id: I5a57f08ea3fce0c78d73aa61b85ff7b0cff450b8
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: David Reguera Garcia (Dreg) <regueragarciadavid@gmail.com >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
2024-08-03 08:37:56 +00:00
d611c31447
doc: Add doc for in-system programming
...
The page on wiki is here:
https://wiki.flashrom.org/ISP
Change-Id: If4752f0f02ae973b3d832f42166de643d95c9f97
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Alexander Goncharov <chat@joursoir.net >
2024-08-03 08:35:20 +00:00
923b6b5b8d
doc: Add page with misc notes and advice
...
This page is a combination of info from the following pages:
https://wiki.flashrom.org/Common_problems
https://wiki.flashrom.org/Connections
https://wiki.flashrom.org/FAQ
https://wiki.flashrom.org/Random_notes
https://wiki.flashrom.org/Live_CD
Change-Id: I538f31765576584760524cd8b06cbf5bce191bde
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83450
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2024-08-03 08:33:03 +00:00
f944a0488d
MAINTAINERS: Add David Reguera for Bus Pirate
...
Change-Id: I0e298732a1464152c0d4cdc728bcdfd1b40ce770
Signed-off-by: David Reguera Garcia <regueragarciadavid@gmail.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2024-08-02 04:41:14 +00:00
ba29ab1e57
manibuilder: Make curl follow redirects
...
The wiki is moving around, and the URLs are probably not final. Until
the download locations can be nailed down to their final location, tell
curl to follow HTTP redirects.
Change-Id: I52f1c786a376f5c7394fa5bffc689e58f8691c75
Signed-off-by: Patrick Georgi <patrick@coreboot.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2024-08-02 00:39:31 +00:00
d3f9c258db
flashchips: add support for chip model Winbond W25Q32JV_M
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This is a 4 MiB model with QE=0 factory setting.
Tested with ch341a programmer: probe, read, write, erase
Link to datasheet:
https://www.winbond.com/resource-files/W25Q32JV%20RevI%2005042021%20Plus.pdf
Change-Id: I374c466848eabf5647dc88e016ac32b99ec37a06
Signed-off-by: Michael Heimpold <mhei@heimpold.de >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2024-07-30 12:28:59 +00:00
e0bc199cde
doc: Add manpage entries for nic3com, gfxnvidia, satasii
...
These programmers have a little information about them on wiki.
It's too little info to create a dedicated page for each
programmer, however info can go to the manpage.
For reference, wiki pages are the following:
https://wiki.flashrom.org/NIC3Com
https://wiki.flashrom.org/Gfxnvidia
https://wiki.flashrom.org/Supported_programmers (search for the
programmers in the table).
Change-Id: Id2a2aefc6a3c8348fdaa4498aaa704fd2da7602f
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83467
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2024-07-26 08:30:59 +00:00
ff656e08e5
flashchips: Add Support for XMC XM25QU512C/XM25QU512D
...
Add initial support for the SPI flash chip XM25QU512C/XM25QU512D
Datasheet link: https://www.xmcwh.com/uploads/808/XM25QU512C_V1.6.pdf
Tested with ch341a programmer: probe, read, write, erase
Change-Id: I251c66b5d3b4fc94242c2c9d6b7c0f03c1bd7d0b
Signed-off-by: Kan Sun <ssunkkan@gmail.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2024-07-26 08:29:13 +00:00
1865ac28a3
flashchips: Add Support for XMC XM25QH512C/XM25QH512D
...
Add initial support for the SPI flash chip XM25QH512C/XM25QH512D
Datasheet link: https://www.xmcwh.com/uploads/803/XM25QH512C_V1.6.pdf
Tested with ch341a programmer: probe, read, write, erase
Change-Id: Ica8ed5eaba2435a9416274b94f633ea40dfeea2f
Signed-off-by: Kan Sun <ssunkkan@gmail.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83242
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2024-07-26 08:28:47 +00:00
a7606f014a
flashchips: Add Support for XMC XM25QU256D
...
Add initial support for the SPI flash chip XM25QU256D (same as XM25QU256C)
Datasheet link:
https://www.xmcwh.com/uploads/224/XM25QU256C%20_%20Ver%202.0.pdf
Tested with ch341a programmer: probe, read, write, erase
Change-Id: I504699160f804cfbacd189409596e105752d94eb
Signed-off-by: Kan Sun <ssunkkan@gmail.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2024-07-26 08:24:57 +00:00
806e76477f
flashchips: Add Support for XMC XM25QH256D
...
Add initial support for the SPI flash chip XM25QH256D (same as XM25QH256C)
Datasheet link:
https://www.xmcwh.com/uploads/802/XM25QH256C%20_%20Ver%202.0.pdf
Tested with ch341a programmer: probe, read, write, erase
Change-Id: I77481e63eb98ed12935288dc0d6286cb1baf8edb
Signed-off-by: Kan Sun <ssunkkan@gmail.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83240
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2024-07-26 08:23:28 +00:00
4465fe6356
flashchips: Add Support for XMC XM25QU128D
...
Add initial support for the SPI flash chip XM25QU128D (same as XM25QU128C)
Datasheet link: https://www.xmcwh.com/uploads/227/XM25QU128C_Ver2.1.pdf
Tested with ch341a programmer: probe, read, write, erase
Change-Id: If5fe2b3c1973599aecb80adcb5f0fe2dec0da0e5
Signed-off-by: Kan Sun <ssunkkan@gmail.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2024-07-26 08:20:18 +00:00
c864c10625
flashchips: Add Support for XMC XM25QH128D
...
Add initial support for the SPI flash chip XM25QH128D (same as XM25QH128C)
Datasheet link: https://www.xmcwh.com/uploads/801/XM25QH128C_Ver2.1.pdf
Tested with ch341a programmer: probe, read, write, erase
Change-Id: Ia4577fba545f9f8eea15eef7060bd5955a8457ca
Signed-off-by: Kan Sun <ssunkkan@gmail.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83238
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2024-07-26 08:19:20 +00:00
3e7d4743ae
flashchips: Add Support for XMC XM25QH64D
...
Add initial support for the SPI flash chip XM25QH64D (same as XM25QH64C)
Datasheet link: https://www.xmcwh.com/uploads/800/XM25QH64C_Ver1.8.pdf
Change-Id: Ia3357cb2c30cbe34dcf0e06fd037064304b4c0c4
Signed-off-by: Kan Sun <ssunkkan@gmail.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2024-07-26 08:17:33 +00:00
029951e08d
flashchips: Add Support for XMC XM25QU32C
...
Add initial support for the SPI flash chip XM25QU32C
Datasheet link: https://www.xmcwh.com/uploads/233/XM25QU32C_Ver2.1.pdf
Tested with ch341a programmer: probe, read, write, erase
Change-Id: Ida0ab895309ef83dcc6b3f03c032a16f9b1f923a
Signed-off-by: Kan Sun <ssunkkan@gmail.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2024-07-26 08:14:16 +00:00
2f7edbf6fe
flashchips: Add Support for XMC XM25QH32C/XM25QH32D
...
Add initial support for the SPI flash chip XM25QH32C/XM25QH32D
Datasheet link: https://www.xmcwh.com/uploads/799/XM25QH32C_Ver2.1.pdf
Tested with ch341a programmer: probe, read, write, erase
Change-Id: Ib201ac28384b8db6539e2a82e6f90462d1393208
Signed-off-by: Kan Sun <ssunkkan@gmail.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2024-07-26 08:10:27 +00:00
7432b540c1
flashchips: Add Support for XMC XM25QU16C
...
Add initial support for the SPI flash chip XM25QU16C
Datasheet link: https://www.xmcwh.com/uploads/804/XM25QU16C_%20Ver1.8.pdf
Tested with ch341a programmer: probe, read, write, erase
Change-Id: I0989b5dd239dd32f93e1a338a70e5d7279127d8d
Signed-off-by: Kan Sun <ssunkkan@gmail.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2024-07-26 08:06:53 +00:00
04d0259ef1
flashchips: Add support for MXIC MX25U25645G
...
The MX25U25645G has been tested by ch341a programmer : read, write,
erase and wp.
We have tested --wp-enable, --wp-disable, --wp-list and --wp-range
commands for write-protect feature.
MX25U25645G datasheet is available at the following URL:
https://www.mxic.com.tw/Lists/Datasheet/Attachments/8738/MX25U25645G,%201.8V,%20256Mb,%20v1.4.pdf
Change-Id: I8641f36e1909274629690fc243be46281a21360d
Signed-off-by: DanielZhang <danielzhang@mxic.com.cn >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/82777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2024-07-26 08:04:02 +00:00
98cff507ca
how_to_add_new_chip: Add a section for feature bits and WRSR handling
...
Feature bits are too complicated to understand if we only read the
codes/datasheets. Add a new section in how_to_add_new_chip to add more
details about each feature bits.
Add the detailed explanation for WRSR handling first. If this new
section looks good, I'll try to add some more sections in further
commits.
BUG=b:345154585
TEST=meson compile -C builddir and view the doc.
Change-Id: I34c20933a375380c8702f79ac637595cd3466000
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/82908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2024-07-26 08:01:24 +00:00
0cf4b46650
flashchips: Add chip models GD25LB256F/GD25LR256F
...
GD25LB256F: 1.8V 256Mbit
https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230926/DS-00978-GD25LB256F-Rev1.0.pdf
GD25LR256F: 1.8V 256Mbit with RPMC.
https://www.gigadevice.com/message-board?cid=39&id=3171&file_type=Datasheet&file_name=GD25LR256F
Tested Erase, write, read, and protection.
Change-Id: I0fbd270a57999d4131816c48470588bb7ec22d37
Signed-off-by: Victor <vlim@gigadevice.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nikolai Artemiev <nartemiev@google.com >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2024-07-26 08:00:03 +00:00
550a172532
VERSION: Update version to 1.5.0-devel
...
Change-Id: Ie273d716f3b16798cdc1207aa28205c176f9156a
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83648
Reviewed-by: Peter Marheine <pmarheine@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2024-07-26 00:10:32 +00:00
551a22216d
doc: Add download info to release notes 1.4.0
...
Change-Id: I9a51c3feff81b405d30f479302e3e75fa0d6803b
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
2024-07-25 07:23:30 +00:00
eace095b15
VERSION: Update version to 1.4.0
...
Change-Id: I16ac300395b70e48e371c04d1fa5d5dad1515112
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83645
Reviewed-by: Peter Marheine <pmarheine@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2024-07-25 02:59:19 +00:00
30c85a62c1
doc: Release notes for version 1.4.0
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Change-Id: Ie5597f1c3ae9289e424f54c2d313fef8efbdf1a0
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83359
Reviewed-by: Peter Marheine <pmarheine@chromium.org >
Reviewed-by: Alexander Goncharov <chat@joursoir.net >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2024-07-25 01:21:26 +00:00
e4e0fd0d82
meson: Fix project name as flashrom
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Change-Id: I08785283a62c21491ac633f6fed43a7dc3fd825a
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83611
Reviewed-by: Peter Marheine <pmarheine@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2024-07-23 06:52:11 +00:00
ee7f3a7658
VERSION: Update version to 1.4.0-rc2
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Change-Id: I725dbbbd43b3b51a5034f5a940ab7a72530bac80
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Peter Marheine <pmarheine@chromium.org >
2024-07-11 01:52:12 +00:00
f67aa6773d
libflashrom.map: remove non-existent functions
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Remove symbol names from the map that do not exist in the code.
https://bugs.gentoo.org/928955
Change-Id: I30bab842d9cbd2daaa9902fd3223f47145cb0e7f
Signed-off-by: Fabian Groffen <grobian@gentoo.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83261
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Peter Marheine <pmarheine@chromium.org >
2024-07-04 22:54:33 +00:00
9bb30822d8
VERSION: Update version to 1.4.0-rc1
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Change-Id: I013a35de898cbd5c09d254baccb3d644c1def2a0
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Peter Marheine <pmarheine@chromium.org >
2024-06-28 02:30:50 +00:00
4b1611afbe
flashchips: Add Support for XMC XM25QH16C/XM25QH16D
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Add initial support for the SPI flash chip XM25QH16C/XM25QH16D
Datasheet link: https://www.xmcwh.com/uploads/798/XM25QH16C_Ver1.8.pdf
Tested with ch341a programmer: probe, read, write, erase
Change-Id: I215084ed33ca9261f6c7b91ef868ca8db85e61ad
Signed-off-by: Kan Sun <ssunkkan@gmail.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83182
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2024-06-27 21:18:18 +00:00
a89d2f906b
flashchips: Add Support for XMC XM25QU80B
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Add initial support for the SPI flash chip XM25QU80B
Datasheet link: https://www.xmcwh.com/uploads/520/XM25QU80B_Ver1.4.pdf
Tested with ch341a programmer: probe, read, write, erase
Change-Id: I8350f4ba94b4819e6496b9c5fddc8617bc0528b5
Signed-off-by: Kan Sun <ssunkkan@gmail.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83180
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2024-06-27 00:50:30 +00:00
9e175cfdda
util/ich_descriptors_tool: Add Panther Lake SoC to supported chipsets
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This change extends the ich_descriptors_tool to recognize and process
descriptors for Intel's upcoming Panther Lake SoC.
BUG=b:347669091
TEST=ich_descriptors_tool is able to detect "panther" chipset and show
below information:
> ./util/ich_descriptors_tool/ich_descriptors_tool
Need the file name of a descriptor image to read from.
usage: './util/ich_descriptors_tool/ich_descriptors_tool -f
<image file name> [-c <chipset name>] [-d]'
...
...
To also print the data stored in the descriptor straps you have to
indicate the chipset series with the '-c' parameter and one of the
possible arguments:
- "ich8",
- "ich9",
- "ich10",
- "apollo" for Intel's Apollo Lake SoC.
- "gemini" for Intel's Gemini Lake SoC.
- "jasper" for Intel's Jasper Lake SoC.
- "meteor" for Intel's Meteor Lake SoC.
- "panther" for Intel's Panther Lake SoC.
...
...
- "300" or "cannon" for Intel's 300 series chipsets.
- "400" or "comet" for Intel's 400 series chipsets.
- "500" or "tiger" for Intel's 500 series chipsets.
- "600" or "alder" for Intel's 600 series chipsets.
Change-Id: I17d616d346daca15b43eb294401ac0c672b64c4a
Signed-off-by: Subrata Banik <subratabanik@google.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83149
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
Reviewed-by: Sam McNally <sammc@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2024-06-27 00:44:21 +00:00
57cd50cd6a
ichspi: Add support for Panther Lake
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This patch adds Panther Lake support into flashrom as per Intel
Panther Lake SPI programming doc, number: 815466.
BUG=b:347669091
TEST=Flashrom is able to detect PTL SPI DID and show chipset name as
below:
> flashrom --flash-name
....
Found chipset "Intel Panther Lake-U/H 12Xe".
....
> flashrom -p internal --ifd -i fd -i bios -r /tmp/bios.rom
....
Reading ich_descriptor... done.
Assuming chipset 'Panther Lake'.
Using regions: "bios", "fd".
Reading flash... done.
SUCCESS
Change-Id: I99cd8eb7cbb11381f8e8455b06cf90b9db77d8f0
Signed-off-by: Subrata Banik <subratabanik@google.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83144
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com >
Reviewed-by: Hsuan-ting Chen <roccochen@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
Reviewed-by: Sam McNally <sammc@google.com >
2024-06-27 00:44:06 +00:00
30d1b5a107
hwaccess_x86_io: Fix Android compilation with bionic libc
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Recently Android Bionic LibC got sys/io.h. Use this header to access
ioperm(). Use Assembly for I/O, as Bionic does not have inb(), outb(),
etc.
Tested on Android 14 by adding flashrom and pciutils as external repositories, adding Android.bp blueprints (Android specialized build system - Soong), building, running and accessing (read, erase, write) SPI flash on x86 device.
Change-Id: Id80b83c2718679c925ed6ddfe33cbe837eea0429
Signed-off-by: Jakub Czapiga <czapiga@google.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83133
Reviewed-by: Peter Marheine <pmarheine@chromium.org >
Reviewed-by: Hsuan-ting Chen <roccochen@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2024-06-27 00:42:14 +00:00
eeb9b5dcf0
flashchips: Set default wp test status for chips with custom config
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Without this, default value is the first in enum, which is OK. While
in reality, for the chips in the patch block-protection is not
available, so should be NA.
wp test status support was introduced later than the others, so old
chips don't have this field initialised.
Change-Id: I6ed8e04cd215865dc6a7d9415634dedbe3014ab5
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83132
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2024-06-25 09:31:42 +00:00
f8e618606a
print.c: Print B (block-protect) test status of the chips
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This also expands the column for test status by 1 more char, since
now maximum status is longer, PREWB vs PREW.
print.c runs when command line option `flashrom -L` is invoked.
Change-Id: If697fe3ba93dbe34bb8f7a9a4b1686fdb8b3ee58
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83131
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2024-06-25 09:31:05 +00:00
d32b487564
flashchips: add GD25LB256E chip model
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adding GD25LB256E to the model GD25LR256E which share the same feature.
The datasheet link
https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230627/DS-00513-GD25LB256E-Rev2.0.pdf
Tested read, write, erase, --wp-enable, --wp-disable, --wp-list and --wp-range
Change-Id: I0aa520b068a86098f6b4a1b68401c425b33e501f
Signed-off-by: Victor Lim <vlim@gigadevice.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83140
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2024-06-25 09:08:41 +00:00
4f3ee6f953
ich_descriptor: Fix chipset_names index for Intel Meteor Lake
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commit hash 85b977151bsubratabanik@google.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83143
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
Reviewed-by: Sam McNally <sammc@google.com >
Reviewed-by: Hsuan-ting Chen <roccochen@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2024-06-24 01:38:19 +00:00
