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3949 Commits

Author SHA1 Message Date
b41fc17099 libflashrom: Deprecate probing v1 API
flashrom_flash_probe marked as deprecated and existing tests are
updated to use probing v2 API

Change-Id: I88f78ac0c93ce99a555b42f87aa0a695089e0b3f
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/88202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
2025-06-30 01:24:47 +00:00
f1f0dd6ab3 cli_classic.c: Reimplement parse_wp_range
Current method modifies the optarg string and
causes it to not get printed in future debug log.

For example writing the log to a file with -o
will show "Command line" without the size
parameter of the range.

Tested by logging the output and reading the log:
./flashrom -p linux_spi:dev=/dev/spidev0.0 -c "W25Q64JV-.Q" \
--wp-range 0x0,0x00001000 -o logfile && grep 'Command line' logfile

Change-Id: I77acd49a5fa17a0af69b4fb1371a131a5249d3dc
Signed-off-by: Nikola Z. Ivanov <zlatistiv@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/88162
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-06-29 04:37:03 +00:00
bc8f7c71b8 flashchips: Mark W25Q64JV-.Q as tested for WP
Tested via linux_spi on raspbery pi
Commands ran and output: https://paste.flashrom.org/view.php?id=3770
Chip datasheet: https://docs.rs-online.com/53b3/0900766b8162304e.pdf
Top side on marking on the chip is 25Q64JVSIQ.

Change-Id: I891a2082e2b662523571d761418860eb4a3f9671
Signed-off-by: Nikola Z. Ivanov <zlatistiv@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/88183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
2025-06-28 08:38:07 +00:00
ed47c87176 jlink_spi: Increase delay on power on feature from 10 to 100 millisec
More delay time is needed to stabilize the LDO and the decoupling
capacitors when power on feature is enabled. Specifically 100 ms
was tested on HT7333 and it's sufficient.

I used the power supply from the J-Link device pin 19.
this power is 5V, I put a 3.3V LDO (HT7333) after it, and this LDO
(and decoupling capacitors) need more time to fix output voltage.

Change-Id: Ic2dd94e99ac6ffa17a009b8488ce027698ae2c28
Signed-off-by: Attila Veghelyi <aveghelyi@dension.com>
Tested-by: Attila Veghelyi <aveghelyi@dension.com>
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/86085
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-06-06 00:13:27 +00:00
1516420f3f fmap: Skip unreadable regions when attempting to locate FMAP
When using the on-chip FMAP to restrict flashrom operations to one or
more regions (--fmap), flashrom must first locate the FMAP. This
requires flashrom to read from multiple addresses, some of which
may be located in regions which are not readable (such as the
Intel ME region). In order to avoid a substantial amount of output from
read_flash() when trying to locate the FMAP in these regions, set
`the skip_unreadable_regions` flag before performing any reads to
locate the FMAP, and restore the original flag value when finished.

This resolves https://ticket.coreboot.org/issues/587

TEST=build flashrom, use cli to update COREBOOT and EC FMAP regions on
an Intel Alderlake-N platform board (starlabs/starlite_adl).

Change-Id: Ie78b977b4e6a5db02a25e69603f697834043ea99
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/87748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
2025-05-22 23:12:01 +00:00
9d6ce34659 doc/devel: Add info about new libflashrom APIs
Change-Id: I98524353b8bedff3364568636ed42a4bd6ce8b3d
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/87644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
2025-05-16 10:22:47 +00:00
0c63f85d7d cli: Remove array of flash contexts, use one active context instead
The only purpose of array of 8 flash contexts was to facilitate
probing of multiple chips. Probing is now done inside libflashrom,
and cli as a client of libflashrom only need to have one active
context.

In addition to array of 8, cli also had one more flash context,
`fill_flash` which is also now replaced by the same, one active
context.

Another detail is that array of 8 was effectively a limit of how
many mathing chips could be found. While 8 seemed a lot at the time
of initial implementation, at the moment we have an example of
6 matches already.
(see `./flashrom -p dummy:emulate=MX25L6436`)

Change-Id: Ia4284ae7aaa43fe59f0d3f57314ebc5cc93d2d9b
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/87533
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-05-12 09:24:51 +00:00
18303f193a libflashrom: Add probing v2 which can find all matching chips
Probing v2 can (if requested) go through all flashchips and find
all the matching chip definitions. This is the way cli behaves,
so cli becomes a client of probing v2.

Previously cli and libflashrom had different probing logic, and
different code in different source files.

This patch also adds tests for probing v2.

Testing from the cli:
./flashrom -p dummy:emulate=W25Q128FV -r dump.rom
./flashrom -p dummy:emulate=MX25L6436 -r dump.rom
./flashrom -p dummy:emulate=MX25L6436 -c "MX25L6473E" -r dump.rom
./flashrom -p dummy:emulate=SST25VF032B -E
./flashrom -p dummy:emulate=S25FL128L -r dump.rom
./flashrom -p dummy:emulate=INVALID -r dump.rom
./flashrom -p dummy:emulate=MX25L6436 -c "NONEXISTENT" -r dump.rom

Change-Id: Idfcf377a8071e22028ba98515f08495ed2a6e9f0
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/87341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
2025-05-12 09:24:34 +00:00
b1f2cb7c1a flashchips: Mark W25Q256JV_Q as tested for read/write/erase
As reported on the mailing list:
https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/Y27HIB5SPMQVGER37RLPV36DW33QGLR4/

Change-Id: I267ee7e86c682626ead2310b920a0e5026982312
Tested-by: Attila Veghelyi <aveghelyi@dension.com>
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/87459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: attila-v
2025-04-30 00:11:59 +00:00
4d4688ccf1 doc: Update supported flashchips page because we split the large file
Change-Id: Ic6179517d0f951a32c0c4e0baf32677398224542
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/86953
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-04-11 00:34:26 +00:00
bc029c2f45 libflashrom: Add API to get the list of supported programmers
There were no options available to obtain the list of programmers.
The implementation is based on flashrom_supported_flash_chips.
Arrays of constant strings are returned, and the array must be
freed using flashrom_data_free.

Testing: Both unit tests and CLI tools serve as libflashrom clients.
    All unit tests run successfully.

Change-Id: Ib5275b742b849183b1fe701900040fee369a1d78
Signed-off-by: Dmitry Zhadinets <dzhadinets@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/86921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
2025-04-10 00:51:35 +00:00
6ff43de0e0 libflashrom: Fix dynamic linkage
flashrom_set_log_level was not added to the map file

Testing: Both unit tests and CLI tools serve as libflashrom clients.
    All unit tests run successfully.

Change-Id: Iaa9f50d79364cd3ba8242e4faea7612c88e7053c
Signed-off-by: Dmitry Zhadinets <dzhadinets@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/87194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
2025-04-10 00:47:35 +00:00
f163f1c692 libflashrom: Set maximum log level SPEW by default
This log level is the maximum level that will trigger the log
callback. By default log callback should be triggered for all
messages, and then client can decide whether they want to lower
the level.

This also keeps the same behaviour for existing clients of
libflashrom, the same as it was before introducing the ability
to set max log level in log callback API.

Follow up on
commit 4e334c4f79

Change-Id: Id063c31e685c930b9f5632c7b86ffac6fe477fd5
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/87180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dmitry Zhadinets <dzhadinets@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2025-04-06 22:52:44 +00:00
79f0d814c2 cli: Set maximum log level for log callback
Follow up (or fix) on
commit 6571f263b5
which adds ability to set maximum log level to log callback API.
And INFO as the default.

Without this patch cli options -V, -VV, -VVV not working anymore.

cli at the moment processes all the messages in the callback,
so log level should be maximum possible to get all the messages.

Alternative to this could be setting the default max log level
for callback as SPEW.

Tested by running with -V, -VV, -VVV
flashrom -p dummy:emulate=W25Q128FV,freq=64mhz -r dump.rom --progress

Change-Id: I70a02ea1a1d692267fd6d92cdb5273786a913777
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/87174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dmitry Zhadinets <dzhadinets@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2025-04-06 00:15:47 +00:00
6571f263b5 libflashrom: Add set log level functionality
Before this commit, any message from Flashrom would trigger
the user's callback. This could lead to additional delays
and slow down overall Flashrom performance.

This patch adds the ability to configure the log level for
messages from Flashrom. It sets the default log level to INFO

Testing: Both unit tests and CLI tools serve as libflashrom clients.
    All unit tests run successfully.

Change-Id: I095d48b8feb5fbc950a36eb17bed0d7cb8d9df64
Signed-off-by: Dmitry Zhadinets <dzhadinets@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/87047
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-04-04 11:35:23 +00:00
b1794138f0 libflashrom: Update the API for Logger Callback
The initial implementation does not account for user_data, requiring
the calling application to use a global scope. This may lead to issues
related to object lifecycle management and other architectural
concerns.

This patch adds user_data to the user’s log callback. Moreover, it
performs message formatting, so the application only needs to pass
the formatted string to the selected output.

The change does not break the existing logging API but extends it.
A new API version is introduced with the v2 suffix.

Testing: Both unit tests and CLI tools serve as libflashrom clients.
    All unit tests run successfully.

Change-Id: Iea738bd371fa3d69b9cf222c89ee67490d30af39
Signed-off-by: Dmitry Zhadinets <dzhadinets@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/86875
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-04-04 11:35:09 +00:00
90cc93d9bb chipset_enable.c: Mark Intel B150 and Q170 as tested
Mark both B150 and Q170 as tested (DEP, as writability depends on the
flash descriptor). B150 was found in a ThinkCentre M700 Tiny, and Q170
in a ThinkCentre M900 Tiny, both support internal flashing once coreboot
is flashed (and coreboot SPI flash lockdown is not enabled).

Change-Id: Iedf4c77e3228628ac1a8726c1a9b4fb733d63d40
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/87045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
2025-04-03 11:28:42 +00:00
0cad6dfd68 flashchips: Add Macronix MX77U25650FZ4I42
Add initial support for Macronix MX77U25650F

Bug=N/A
TEST=build flashrom and read/write/earse on unit works
e.g. command:
flashrom -p raiden_debug_spi:target=AP -w image.bin
flashrom --read -o image.bin
futility update/read

Change-Id: I7866b2db343f4eb2bc194400ceca099d3af3b87d
Signed-off-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/86348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: DZ <danielzhang@mxic.com.cn>
2025-03-31 06:25:54 +00:00
505c259ca8 flashchips: Add XMC XM25QH64A
Based off of the now-abandoned GitHub pull request here:
https://github.com/flashrom/flashrom/pull/239

Datasheet:
https://www.micros.com.pl/mediaserver/PFXM25QH64AHIG_0001.pdf

This commit applies the changes on top of the refactor where the flash
chip declarations were separated by vendor.

Change-Id: I5b11e30f0a5357a6cbb32ddb93f450de5364c60b
Co-authored-by: Ayushman Dutta <ayushman999@gmail.com>
Co-authored-by: "aiyion.prime" <git@aiyionpri.me>
Co-authored-by: Eric Park <me@ericswpark.com>
Signed-off-by: Eric Park <me@ericswpark.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/86990
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-03-29 22:17:56 +00:00
81c21880a3 spidriver: Add support for the Excamera Labs SPIDriver programmer
This is a SPI hardware interface with a display (https://spidriver.com/),
connected as an FT230X USB serial device at a fixed baud rate of 460800.

Firmware: https://github.com/jamesbowman/spidriver
Protocol: https://github.com/jamesbowman/spidriver/blob/master/protocol.md

Most of the implementation is copied from the Bus Pirate programmer.

Tested with a SPIDriver v2 by reading FM25Q128A flash memory on Linux.

Change-Id: I07b23c1146d4ad3606b54a1e8dc8030cf4ebf57b
Signed-off-by: Simon Arlott <flashrom@octiron.net>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/86411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
2025-03-26 21:56:00 +00:00
c3b89597fc flashchips/winbond: Update test status for Winbond W25Q128.JW.DTR
Tested probe, read, erase, write, and WP operations on a Winbond
W25Q128.JW.DTR chip using internal and raiden_debug_spi programmers.

Change-Id: Ie2fdb2c305dca3677950cc6855d41b7161a0fce9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/86848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
2025-03-16 21:58:33 +00:00
b169da4edb tests/chip: fix print format errors in gcc 14.2.0
Change-Id: I8c461accefddce3d5ee33b0fb6b91c434d721945
Signed-off-by: Antonio Vázquez Blanco <antoniovazquezblanco@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/86679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2025-03-16 10:41:26 +00:00
4054920f09 doc: Final cleanup of remaining references to the old wiki website
Change-Id: Ie002c1242075c8becb59d26bd9c562c7616233c1
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/86676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2025-03-09 07:34:53 +00:00
e2df58a379 libflashrom: Update the API for progress callback
The initial version of API for progress callback would require the
callback function to make a second call to get the needed data about
progress state (current, total etc).

This patch changes the callback API, so that callback function gets
all needed data straight away as parameters, and with this,
callback has all the data to do its job.

Since the initial version was submitted and it was in the tree for a
while, the change needs to add a _v2 suffix for new thing and
deprecated attribute for old thing.

Testing: both unit tests and cli are libflashrom clients.
All unit tests run successfully, for the cli all scenarios from
commit 75dc0655b9 run successfully.

Change-Id: Ia8cc0461c449b7e65888a64cdc594c55b81eae7a
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/86031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
2025-03-09 07:34:06 +00:00
f5a3c7a35b util/docker: Update the script that updates the website
- Update the base system (alpine 3.8 -> 3.21)
- Update sphinx and its modules (and from pip-install to alpine-install)
- Remove unused features that increase maintenance overhead
  (autobuild/livehtml and ditaa)
- Use the build system to generate docs (instead of calling sphinx in
  its own, custom ways)

Change-Id: I844e4ea84b94444c96f29325fee205b0deb972da
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/86681
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-03-06 10:12:19 +00:00
73666de3f2 Enable authors list generation on Jenkins
Change-Id: Ia018ce4addb65273fe022ed1f1e9d38420c0e469
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/86678
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-03-06 02:35:40 +00:00
0b39a3e00c doc: autogenerate a list of authors and hall of fame
This adds a build-time option to automatically generate a list of
authors from git history, and includes it in the documentation by
reading the output from git in a Sphinx extension. When git isn't
available or the project source doesn't appear to be a git checkout, the
list is not generated and gracefully replaced with a message explaining
its absence.

Change-Id: I1e9634a90e84262aafd80590deba9875f4b71a3c
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/86350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
2025-02-28 03:56:40 +00:00
07beef6999 doc: Add useful links to README
Change-Id: Ib231150acd8aa911d534f67ff1ce937c6963812c
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/86430
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-02-24 06:50:19 +00:00
927b5adbe6 doc: Add missing step in the beginning of building from source doc
Change-Id: Id834d3de69c038f3cc1aee3c59c3607f42fd5b49
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/86429
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-02-24 06:50:10 +00:00
b7ed1634b8 doc: Remove reference to coreboot dev guidelines
The guidelines are fully specified on flashrom.org, no need to
reference them.

Change-Id: If5fbcf1f4dc00dd1a9c48e9fad6c99d646954bfb
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/86547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
2025-02-24 06:47:57 +00:00
49e33c8939 doc: Point to web page instead of Wiki for Laptops page
There were three occurences pointing to the retired wiki instead
of the web page https://flashrom.org/contrib_howtos/laptops_and_ec.html

Change-Id: I62950e1099183171dd3b94200014034b0616a4b4
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/86546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
2025-02-24 06:47:34 +00:00
5e56f42eaa doc: Point to correct kernel coding style
Right now it points to the source of the page instead of the
actual page.

Change-Id: Ib52de1312419cc48478fb965ccb104bdb0dea9b6
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/86545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
2025-02-24 06:47:12 +00:00
4c6df1e168 flashchips/winbond: Update test status for Winbond W25Q128.W
Tested probe, read, erase, write, and WP operations on a Winbond
W25Q128.W chip using internal and ch341a_spi programmers.

Change-Id: Ia1f2a5f4942a4f1956405afa5b56c9e38101f2be
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/86544
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-02-24 06:43:36 +00:00
ce825859c4 Move SPI declarations from flash.h to spi.h
As a consecuence, some of the files that used to include flash.h no
longer need to do so. For this reason, flash.h includes are also deleted
in this commit.

Change-Id: I794a71536a3b85fde39f83c802fa0f5dd8d428e0
Signed-off-by: Antonio Vázquez Blanco <antoniovazquezblanco@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/85539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-by: David Reguera Garcia (Dreg) <regueragarciadavid@gmail.com>
Reviewed-by: Matti Finder <matti.finder@gmail.com>
2025-02-21 07:17:57 +00:00
971ea27d16 doc: Migrate collection of docs about board enable
Collection is gathered from these docs:
https://wiki.flashrom.org/Board_Enable
https://wiki.flashrom.org/Board_Testing_HOWTO
https://wiki.flashrom.org/Finding_Board_Enable_by_Reverse_Engineering

Change-Id: I0aaa39679514f667c70ba50f6b726e8d1bd07825
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/86329
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-02-12 23:37:46 +00:00
9ef4da746b doc: Migrate doc about raspberry pi
Old doc:
https://wiki.flashrom.org/RaspberryPi

Change-Id: Ie3b7f2ed31f0b756815de055a2c58602263dac66
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/86312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2025-02-12 23:37:31 +00:00
ed84669d9f doc: Migrate old pages about laptops and EC
Old pages are:
https://wiki.flashrom.org/Laptops
https://wiki.flashrom.org/Laptop_enable

Info from both is gathered into one doc.

Change-Id: I26f5aef8d679d37fcaebfd830a04d09d818ffe0b
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/86243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2025-02-05 11:17:45 +00:00
b9cb629956 doc: Migrate privacy policy page from old website into new one
Change-Id: I54ace480b3bebe3031ea6d1e507c540ac1dc7cc6
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/86242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2025-02-04 08:20:12 +00:00
1b9bcdc99b flashchips/winbond.c: Add reg_bits for W25Q256JW
Add reg_bits for W25Q256JW as per the datasheet. The register
definitions are same as W25Q256JW_DTR.

Datasheet: https://www.winbond.com/hq/support/documentation/levelOne.jsp?__locale=en&DocNo=DA00-W25Q256JW

BUG=b:376929528
TEST=Program and verify WP ranges

```
flashrom -p internal --wp-status
flashrom -p internal --wp-range 0x0,0x2000000
flashrom -p internal --wp-enable
flashrom -p internal --wp-status
```

Change-Id: I050754b28a90911a50f891869297524ce9a6720e
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/85323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2025-02-03 08:06:10 +00:00
15e6b33743 doc: Add recent entries into Recent development doc
Normally the info would be added in the same patch, but these efforts
were ongoing in parallel with release prep, which makes it hard to
modify devel.rst at the same time.

Change-Id: Ic852df125c9740d95dc1b9ad8ad97bfd56d40211
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/86060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2025-01-23 22:21:22 +00:00
1deeb5d392 doc: Add document for using flashrom with CH341A/B
Document is contributed by Stephan Schneider.

Change-Id: Id6848329d88146fc8a005437a76ec52bec986259
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/86019
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-01-20 02:39:21 +00:00
5ffbe0da88 flashchips/winbond: Update test status for Winbond W25Q256JV_M
Tested probe, read, erase, write, and WP operations on a Winbond
W25Q256JV_M chip using internal and raiden_debug_spi programmers.

Change-Id: I48f37665c9578c4fdb360111f20958fbccc51a37
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/85896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
2025-01-12 08:11:36 +00:00
52a495b443 flashchips: Add Spansion S25FS512S
Tested probe, read, erase, write on FS512SAIF01 chips
using Linux SPI and DediProg SF100 programmers.

This change affects S25FL512S identification as well,
so that both chips can be unambiguously detected by probing.

Datasheets used:
* Infineon-S25FS512S_512_Mb_1-DataSheet-v16_00-EN.pdf
    at https://www.infineon.com/dgdl/?fileId=8ac78c8c7d0d8da4017d0ed681a356fe
* Infineon-S25FL512S_512_Mb_64_MB_FL-S_Flash_SPI_Multi-I_O_3-DataSheet-v21_00-EN.pdf
    at https://www.infineon.com/dgdl/?fileId=8ac78c8c7d0d8da4017d0ed046ae4b53

Change-Id: I40b6c081ec7d57eac4f6d2b69cea3878bc92bb47
Signed-off-by: Anton Samsonov <devel@zxlab.ru>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/85585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
2025-01-08 11:35:47 +00:00
2e6b0510cf Add Glasgow to supported serprog programmers documentation
Updated the serprog overview page with info about the Glasgow
Interface Explorer as a valid programmer.

Wasn't able to test as the project wouldnt compile with meson for me
(MacOS 15.1) but tried to make it as similar as possible to what was
already there.

Change-Id: Iabcec27dd675485c69875178858c604ce5c3da29
Signed-off-by: Cattus QQ <cattusqq@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/85527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
2024-12-24 07:31:37 +00:00
2e8ee7c0f5 doc: Add section about v1.5.1 into release notes
Change-Id: Iea0a8a388d74f4e1ad7e9630413d4a5affc755fe
Original-Change-Id: I80f8423133bf779093d57ea6928f09d9d377d20e
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/85655
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/85698
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-12-22 10:27:17 +00:00
b184e013e2 ichspi: Check whether chipset is locked when probing opcode
This is follow up (or fix) for
commit 26a1eb514c

When probing opcode, all opcodes in POSSIBLE_OPCODES are reported as
supported, even if the opcode is not in curopcodes. This is relying
on reprogramming on-the-fly to handle the gap between POSSIBLE_OPCODES
and curopcodes. However, for locked chipsets on-the-fly is not
happening (is not possible, since list of opcodes is locked), so we
can't rely on it.
So, we need to check whether chipset is locked.

Ticket: https://ticket.coreboot.org/issues/573

Change-Id: I701a86f030cfef43a1158bf075287ade569254e6
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Tested-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/85592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-12-18 06:02:43 +00:00
225241817e Extract programmer declarations to the correct header
Change-Id: Ib37b33417154f666d7f72a904381cdf32f6ecc77
Signed-off-by: Antonio Vázquez Blanco <antoniovazquezblanco@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/85538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
2024-12-15 21:56:41 +00:00
b792b44e14 Extract cli_output declarations to a separate header.
This is a simple refactor that aims to simplify maintenance and to
clarify file dependency inside the project.
Currently, many declarations reside in flash.h making it difficult to
really understand file dependency.

Change-Id: I4209d5ed205ca14c39e83aa923e103b7282a7059
Signed-off-by: Antonio Vázquez Blanco <antoniovazquezblanco@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/85134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
2024-12-06 06:30:09 +00:00
e15c1783e7 doc: Double-clarify that mailing list is public
Change-Id: Id8e0daf75e25e6153a80fb9444547bdf91d1d343
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/85277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2024-12-06 06:18:12 +00:00
b9e0a3ce70 cli_classic.c: Make -r/-w/-v argument optional when using -i
Make the filename parameter directly following -r/-w/-v optional, since
the -i parameter allows the image to be written to be sourced from
multiple files, regions to be read from flash and written to separate
image files, and regions to be verified using an image file only
containing that region.

Since the filename parameter following -w/-v was ignored when a
filename was specified following `-i <region>:<filename>`, this patch
essentially removes the requirement to provide an unused parameter.

Based on https://review.coreboot.org/c/flashrom/+/52362.

TEST=run the following commands on a supported board:
flashrom -p internal -r /tmp/coreboot.rom
flashrom -p internal -r --ifd -i bios:/tmp/coreboot.rom
flashrom -p internal -r /tmp/coreboot.rom --ifd -i bios:/tmp/bios.bin
flashrom -p internal -w /tmp/coreboot.rom
flashrom -p internal -w --ifd -i bios:/tmp/coreboot.rom
flashrom -p internal -w /tmp/coreboot.rom --ifd -i bios:/tmp/bios.bin
flashrom -p internal -v /tmp/coreboot.rom
flashrom -p internal -v --ifd -i bios:/tmp/coreboot.rom
flashrom -p internal -v /tmp/coreboot.rom --ifd -i bios:/tmp/bios.bin

Change-Id: I6eba095d478f1a7bdbc3854627a656f93dd9e452
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/85159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
2024-12-06 06:15:56 +00:00