According to the W25Q64JW datasheet rev. E, only devices ending with the
letter 'M' have a device ID of 8017h. There are other variants with
different device IDs. This patch makes the 'W25Q64JW...M' definition
consistent with the 'W25Q32JW...M' definition.
The device ID macro defined in flashchips.h has also been renamed from
WINBOND_NEX_W25Q64JW to WINBOND_NEX_W25Q64JW_M.
BUG=b:166294558
BRANCH=none
TEST=builds
Change-Id: Ib0dc914da286a191d22e666332b1063b88db4251
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/54291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
The chip was added to cros flashrom in
`commit 1fc77dd1ee27a5d6e58a82c6ed6ed390a15372d7`.
Quoting from the commit message:
> We have varied the correct chip name is reported as well as
> write and read 16MBytes of random data and verified the checksum's match.
> Further, --wp-list appears to report the correct ranges.
>
> BUG=b:130199963
> BRANCH=none
> TEST=Ran flashrom with a Dediprog SF100, RW random data and checksum matched.
Change-Id: I7425e12658dd69c4ec8d3309dd591d09a935bb4d
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/53946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Looks like BoHong Microelectronics has the same vendor ID and makes very
similar chips. For instance, Boya BY25Q128AS and BoHong BH25Q128AS have
the same specifications and their datasheets are mostly identical.
Change-Id: I8d6951797daeeecca6af200c995297c0394adefd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52550
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The chip was marked as TESTED_OK_PREW in the cros tree by
`commit 419e32ae457cc36b03757b89471a7ce3770e9611`.
Quoting from the original commit message:
> TEST=Tested writes using Servo
Change-Id: Id7f44a41d6b2c397f1ce2e345f8ab44e95e4cfa2
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/51736
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The chip was marked as TESTED_OK_PREW in the cros tree by
`commit b2f900273aac329b82089e4dbc5a8ba3d032fff0`.
Quoting from the original commit message:
> TEST=read and write BIOS on glimmer with Eon device.
Change-Id: I13dc3e6bde9e4581fdd5856a412918784b913fbc
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/51734
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The following adds support for the Adesto AT25SF128A-SHB-T part.
We have varied the correct chip name is reported as well as write
and read 16MBytes of random data and verified the checksum's match.
Further, --wp-list appears to report the correct ranges.
BUG=None
BRANCH=none
TEST=Ran flashrom with a Dediprog SF100, RW random data and checksum
matched.
Original-Change-Id: Ic22ca588f33753fdf492e8445324bcc0a809d3e2
Original-Signed-off-by: Edward O'Callaghan <quasisec@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/1593201
Original-Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Original-Tested-by: Martin Roth <martinroth@chromium.org>
Original-Reviewed-by: Martin Roth <martinroth@chromium.org>
(cherry picked from commit 1fa87e058b72a2de1e9127a45e9978361de48479)
Note: this does not include the changes made to writeprotect.c in the
original patch, as they depend on a large amount of additional
writeprotect code that is currently only present in the cros tree, and
the intention here is just to reduce the diff in flashchips.c.
The `.wp` field has also been removed.
Change-Id: I1ce2a6699a1f0116306f668123673a1ba9c932d2
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/51097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This patch adds a support of 4-byte address format for VARIABLE_SIZE
dummy flash device, so that it can emulate an flash size larger than
16 MBytes.
- assigned a feature bits FEATURE_4BA to VARIABLE_SIZE flash config.
- added codes handling two commands, JEDEC_READ_4BA and
JEDEC_BYTE_PROGRAM_4BA.
- changed blockeraser to use Chip-Erase command so that it can be
free from flash address byte format.
TEST=ran the command line below:
$ flashrom -p dummy:image=${TMP_FILE},size=33554432, \
emulate=VARIABLE_SIZE -w ${IMG_32MB} -V -f
$ flashrom -p dummy:image=${TMP_FILE},size=16777216, \
emulate=VARIABLE_SIZE -w ${IMG_16MB} -V -f
$ flashrom -p dummy:image=${TMP_FILE},size=8388608, \
emulate=VARIABLE_SIZE -w ${IMG_8MB} -V -f
Signed-off-by: Namyoon Woo <namyoon@google.com>
Change-Id: Ia59eecfcbe798d50f8dacea98c3c508edf8ec77e
Reviewed-on: https://review.coreboot.org/c/flashrom/+/44881
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is designed for firmware updater to pack firmware image
preserving some specific partitions in any size.
BUG=none
TEST=ran the command line below:
$ flashrom -p dummy:image=${TMP_FILE},size=16777216, \
emulate=VARIABLE_SIZE -w ${IMG} -V -f
$ flashrom -p dummy:image=${TMP_FILE},size=auto, \
emulate=VARIABLE_SIZE -w ${IMG} -V -f
Signed-off-by: Namyoon Woo <namyoon@google.com>
Change-Id: Iff266e151459561b126ecfd1c47420b385be1db2
Reviewed-on: https://review.coreboot.org/c/flashrom/+/44879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
W25Q256JW currently has two variants, the W25Q256JW with device
ID 0x6019 added in commit be4682d and the W25Q256JW_DTR (aka
W25Q256JW-IM) with device ID 0x8019 added by this patch.
Winbond W25Q256-series chips have a few device IDs:
0x4019: W25Q256FV
0x6019: W25Q256JW
0x7019: W25Q256JV
0x8019: W25Q256JW_DTR
Hence we need to be more specific with naming than usual to avoid a
false positive with wildcards.
Change-Id: I50a6de2c915f9201c458378fcc49130ead73d8c4
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/42386
Reviewed-by: Simon Buhrow
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds support for the Winbond W25X05CL SPI flash chip. The
Winbond W25X05CL is a 512Kib (64 KiB) SPI flash chip with 4KiB sectors.
I have tested this patch with a Bus Pirate (v3b) and an in-circuit W25X05CL
flash chip using a test clip. Reading, erasing, and writing all function
as expected.
Change-Id: I19c33c7da374f0263f30577a10a0f0f1afa4febc
Signed-off-by: Jacob Appelbaum <jacob@appelbaum.net>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/43573
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit a3519561bd.
Breaks support for most SPI flash chips. It's too big and too
invasive to be reviewed as a single commit.
The changes to `spi_poll_wip():spi25.c` were not noticed in the
original review that were from the similarly named function and
file `s25f_poll_status():s25f.c` in the downstream Chromium fork.
V.2: Rebase and rephrase commit msg to reflect how the issue
slipped in.
Change-Id: Id2a4593bdb654f8a26957d69d52189ce61621d93
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shiyu Sun <sshiyu@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This may seem too big just to support yet another flash chip, but in
reality it brings support for whole new family of S25FS
Spansion/Cypress flash chips. These chips require handling of some
special status registers for erasing or writing, with very specific
timing checks in place.
For example, WIP status bit will remain being set to 1 if erase or
programming errors occur, and in that case chip 'software reset' has
to be performed otherwise the chip will remain unresponsive to all
further commands. Also, special CR3NV register (Configuration Register
3 Nonvolatile) status bits needs to be read and set by using RDAR
(ReaD Any Register) and WRAR (WRite Any Register) OP commands, and
these states are needed to determine which type of reset feature is
enabled at the time (legacy or S25FS type) in the first place,
determine whether Uniform or Hybrid sector architecture is used
at the time, or set programming buffer address wrap point (256 or 512
bytes). Furthermore, S25FS chip status register has to be restored to
its original state (hence that ugly CHIP_RESTORE_CALLBACK) following
erasing or writing, failing to do so may result in host being unable
to access data on the chip at all.
Finally, although this brings support for the whole family of chips,
I only have one such chip to do the actual testing, S25FS128S (Small
Sectors), which I had fully tested on ch341a and FT4232H programmers,
with confirmed working probe, read, erase and write.
Full summary of changes are here:
flashchips:
add new flashchip sctructure property:
.reset
add chip definitions:
S25FS128S Large Sectors
S25FS128S Small Sectors
flash:
add macro (chip_restore_func_data call-back):
CHIP_RESTORE_CALLBACK
flashrom:
add struct:
chip_restore_func_data
add call-back function:
register_chip_restore
spi:
add OP codes:
CMD_RDAR, CMD_WRAR, CMD_WRAR_LEN, CMD_RSTEN, CMD_RST
add register bit function definitions:
CR3NV_ADDR, CR3NV_20H_NV
add timers:
T_W, T_RPH, T_SE
spi25:
refactor (based on chromiumos implementation) function:
spi_poll_wip
port these functions from chromiumos:
probe_spi_big_spansion
s25fs_software_reset
s25f_legacy_software_reset
s25fs_block_erase_d8
spi25_statusreg:
port these functions from chromiumos:
spi_restore_status
s25fs_read_cr
s25fs_write_cr
s25fs_restore_cr3nv
Most of the ported functions are originally from s25f.c found at
https://chromium.googlesource.com/chromiumos/third_party/flashrom
with exception of spi_restore_status which is defined in
spi25_statusreg.c. The rest of macros and OP codes are defined in
same files as in this commit.
Change-Id: If659290874a4b9db6e71256bdef382d31b288e72
Signed-off-by: Samir Ibradzic <sibradzic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This adds missing voltage and capacity variants for N25Q and MT25Q
series devices. This also fixes a typo in some model numbers where the
last letter should have been a G instead of an E. Added devices include:
N25Q256..1E
N25Q512..1G
N25Q00A..1G
N25Q00A..3G
MT25QU128
MT25QL128
MT25QU256
MT25QU512 tested by Jacob Creedon <jcreedon@google.com>
MT25QL01G tested by Konstantin Grudnev <grudnevkv@gmail.com>
MT25QU01G
MT25QL02G
MT25QU02G
Two have been tested as indicated, all other variants added are marked
untested.
Signed-off-by: Jacob Creedon <jcreedon@google.com>
Change-Id: I85630e4f6c0aa3b261f9871b7d363dad278b997e
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Automotive 2 Mbit (256KiB) serial SPI bus EEPROM
PREW tested successfully with use of ch341a programmer
on Linux host 5.2.0-1-MANJARO x86_64
Signed-off-by: Konstantin Grudnev <grudnevkv@gmail.com>
Change-Id: Ic29cd9051c7eac4822d620c299834134f987f01b
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Mark Winbond W25Q40EW as TESTED_PREW.
The Winbond W25Q40EW has been marked TESTED_PREW in the ChromiumOS
repository. ChromiumOS has the same defintion for this chip as this
repo, except that ChromiumOS does not have FEATURE_OTP.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: I4be5b2e1069a3f735f0dc6ec92d5f4c8946fbb02
Reviewed-on: https://review.coreboot.org/c/flashrom/+/35535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Mark EN29F002(A)(N)B as tested for erase and write. This chip was marked
tested in the Chromium (downstream) repo change
98d917cfba55b68516cdf64c754d2f36c8c26722 "Add a bunch of new/tested
stuff and various small changes 8"
TEST=Build and run flashrom -L
Signed-off-by: Alan Green <avg@google.com>
Change-Id: Idd26187905f389fc858eea5b13915af88e40afe9
Reviewed-on: https://review.coreboot.org/c/flashrom/+/35092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Renamed GigaDevice GD25Q128 to GD25Q127C/GD25Q128.
According to downstream (ChromiumOS) change
4216ba3d0fbd1804a71002b9c17e0b04029a03f1 "flashchips: Add GD25Q127C name
to the GD25Q128C entry", the 127C chip is replacement for the 128C chip.
I have confirmed that 127C is newer and that 128C does not appear to be
documented on Gigadevice's website or available from Digikey.
TEST=Ran flashrom -L
Signed-off-by: Alan Green <avg@google.com>
Change-Id: I3366e5904eff2443fda90552f7f5e31a8785d8b3
Reviewed-on: https://review.coreboot.org/c/flashrom/+/35089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Put entry for Unknown SFDP-capable chip back into place at end of file.
Change 1f9cc7d899 "flashchips.c: Sort file
by vendor and model" reordered many entries in flashchips.c, including
this one. However, the entry for Unknown, SFDP-capable chip should not
have been moved before any specific chip entries.
As reported by Angel Pons <th3fanbus@gmail.com> at
https://review.coreboot.org/c/flashrom/+/33931:
"""
Oops, this introduced a bug: the SFDP entry is no longer at the end of
flashchips.c, so probing on a SFDP-capable Winbond chip results in added
noise (flashrom says things about an unknown chip, and then has two
definitions for the same chip).
"""
Signed-off-by: Alan Green <avg@google.com>
Change-Id: I5955020456dbcd5e7db280a459b668a743e464dc
Reviewed-on: https://review.coreboot.org/c/flashrom/+/35037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Change name of GD25LQ128 to GD25LQ128CD. This is an upstreaming of the
change from the chromium flashrom repo SHA
6c957d745f5d3dcadd1035734a5cf1b804bd0f2f (Also visible at
https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/1181175)
The rationale from that change was:
The GD25LQ128C part is EOL. It's replacement is GD25LQ128D, but
both chips identify in the same manner. Add GD25LQ128D to the name
of the part so that it doesn't confused people.
Making this name consistent will simplify further merging from the
chromium fork.
Change-Id: I57804f1a33170668e029a7b08ac050d9a3bd6dbb
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
The MT25Q is the successor to the N25Q from Micron/Numonyx/ST. The MT25Q
is almost entirely backwards compatible with the N25Q series, however,
the MT25Q has additional subsector erase commands available, and there
are differences in stacked devices in the higher capacity variants. The
N25Q devices are left with "Micron/Numonyx/ST" as the vendor and MT25Q
devices are set with "Micron" as the vendor.
Signed-off-by: Jacob Creedon <jcreedon@google.com>
Change-Id: I9d79978544b19cf9acd5f3ea6196cf6f3b3435ef
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
