W25Q256JW currently has two variants, the W25Q256JW with device
ID 0x6019 added in commit be4682d and the W25Q256JW_DTR (aka
W25Q256JW-IM) with device ID 0x8019 added by this patch.
Winbond W25Q256-series chips have a few device IDs:
0x4019: W25Q256FV
0x6019: W25Q256JW
0x7019: W25Q256JV
0x8019: W25Q256JW_DTR
Hence we need to be more specific with naming than usual to avoid a
false positive with wildcards.
Change-Id: I50a6de2c915f9201c458378fcc49130ead73d8c4
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/42386
Reviewed-by: Simon Buhrow
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds support for the Winbond W25X05CL SPI flash chip. The
Winbond W25X05CL is a 512Kib (64 KiB) SPI flash chip with 4KiB sectors.
I have tested this patch with a Bus Pirate (v3b) and an in-circuit W25X05CL
flash chip using a test clip. Reading, erasing, and writing all function
as expected.
Change-Id: I19c33c7da374f0263f30577a10a0f0f1afa4febc
Signed-off-by: Jacob Appelbaum <jacob@appelbaum.net>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/43573
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Nicklas Lennert wrote me via the flashrom mailing list that
he successfully ran read, write and verify cmd.
Signed-off-by: Simon Buhrow <simon.buhrow@posteo.de>
Change-Id: I3608945a38b5ed42b8b2b9b2b388cdea97141d7b
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This reverts commit a3519561bd0fb44153bb376322b799000657576f.
Breaks support for most SPI flash chips. It's too big and too
invasive to be reviewed as a single commit.
The changes to `spi_poll_wip():spi25.c` were not noticed in the
original review that were from the similarly named function and
file `s25f_poll_status():s25f.c` in the downstream Chromium fork.
V.2: Rebase and rephrase commit msg to reflect how the issue
slipped in.
Change-Id: Id2a4593bdb654f8a26957d69d52189ce61621d93
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shiyu Sun <sshiyu@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This may seem too big just to support yet another flash chip, but in
reality it brings support for whole new family of S25FS
Spansion/Cypress flash chips. These chips require handling of some
special status registers for erasing or writing, with very specific
timing checks in place.
For example, WIP status bit will remain being set to 1 if erase or
programming errors occur, and in that case chip 'software reset' has
to be performed otherwise the chip will remain unresponsive to all
further commands. Also, special CR3NV register (Configuration Register
3 Nonvolatile) status bits needs to be read and set by using RDAR
(ReaD Any Register) and WRAR (WRite Any Register) OP commands, and
these states are needed to determine which type of reset feature is
enabled at the time (legacy or S25FS type) in the first place,
determine whether Uniform or Hybrid sector architecture is used
at the time, or set programming buffer address wrap point (256 or 512
bytes). Furthermore, S25FS chip status register has to be restored to
its original state (hence that ugly CHIP_RESTORE_CALLBACK) following
erasing or writing, failing to do so may result in host being unable
to access data on the chip at all.
Finally, although this brings support for the whole family of chips,
I only have one such chip to do the actual testing, S25FS128S (Small
Sectors), which I had fully tested on ch341a and FT4232H programmers,
with confirmed working probe, read, erase and write.
Full summary of changes are here:
flashchips:
add new flashchip sctructure property:
.reset
add chip definitions:
S25FS128S Large Sectors
S25FS128S Small Sectors
flash:
add macro (chip_restore_func_data call-back):
CHIP_RESTORE_CALLBACK
flashrom:
add struct:
chip_restore_func_data
add call-back function:
register_chip_restore
spi:
add OP codes:
CMD_RDAR, CMD_WRAR, CMD_WRAR_LEN, CMD_RSTEN, CMD_RST
add register bit function definitions:
CR3NV_ADDR, CR3NV_20H_NV
add timers:
T_W, T_RPH, T_SE
spi25:
refactor (based on chromiumos implementation) function:
spi_poll_wip
port these functions from chromiumos:
probe_spi_big_spansion
s25fs_software_reset
s25f_legacy_software_reset
s25fs_block_erase_d8
spi25_statusreg:
port these functions from chromiumos:
spi_restore_status
s25fs_read_cr
s25fs_write_cr
s25fs_restore_cr3nv
Most of the ported functions are originally from s25f.c found at
https://chromium.googlesource.com/chromiumos/third_party/flashrom
with exception of spi_restore_status which is defined in
spi25_statusreg.c. The rest of macros and OP codes are defined in
same files as in this commit.
Change-Id: If659290874a4b9db6e71256bdef382d31b288e72
Signed-off-by: Samir Ibradzic <sibradzic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
BUG=b:153515968
BRANCH=kukui
TEST=flash coreboot on kakadu and get successful result.
Change-Id: I8637129421a3b0f96bd8dffa4f50783ea6931967
Signed-off-by: Scott Chao <scott.chao@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40275
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: Edward O'Callaghan <quasisec@chromium.org>
Support GD25WQ80E, which is the internal flash of IT81202.
TEST=Building flashrom and flashing FW image into IT81202 successfully.
Change-Id: Ib5feaa6ecc7b11b2218e5f02c087b4331388bef8
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
32Mbit (4MiB) [x1/x2/x4] Wide Voltage Range (VCC 1.65V-3.6V). It is
similar to the already-supported MX25R6435F, but the total size is
halved.
Tested on ch341a, FT4232H and FT2232H (PicoTAP) programmers, confirmed
working probe, read, erase and write.
Fixes: https://github.com/flashrom/flashrom/issues/43
Change-Id: I6e79115adba17d13d24bc85d78707d53fd4a0be5
Signed-off-by: Samir Ibradzic <sibradzic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit adds support for the Adesto AT25SF321 SPI flash chip. Probe
and read operations have been tested via FT2232H interface, but writes
have not been verified.
Datasheet is available at the following URL:
https://www.adestotech.com/wp-content/uploads/DS-AT25SF321_047.pdf
Change-Id: I7410815e063ffe154a97d7ea5881c8eb82025f56
Signed-off-by: Peter Adkins <pete@kernelpicnic.net>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/36904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Port the code from chromeos flashrom
BUG=b:144297264
TEST=Tested using W25Q128JWDTR in SPI mode
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Ifc28878b17dc10da2cfd8f82fffbd57adb22799e
Reviewed-on: https://review.coreboot.org/c/flashrom/+/36717
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds missing voltage and capacity variants for N25Q and MT25Q
series devices. This also fixes a typo in some model numbers where the
last letter should have been a G instead of an E. Added devices include:
N25Q256..1E
N25Q512..1G
N25Q00A..1G
N25Q00A..3G
MT25QU128
MT25QL128
MT25QU256
MT25QU512 tested by Jacob Creedon <jcreedon@google.com>
MT25QL01G tested by Konstantin Grudnev <grudnevkv@gmail.com>
MT25QU01G
MT25QL02G
MT25QU02G
Two have been tested as indicated, all other variants added are marked
untested.
Signed-off-by: Jacob Creedon <jcreedon@google.com>
Change-Id: I85630e4f6c0aa3b261f9871b7d363dad278b997e
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Automotive 2 Mbit (256KiB) serial SPI bus EEPROM
PREW tested successfully with use of ch341a programmer
on Linux host 5.2.0-1-MANJARO x86_64
Signed-off-by: Konstantin Grudnev <grudnevkv@gmail.com>
Change-Id: Ic29cd9051c7eac4822d620c299834134f987f01b
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Take definition of GD25Q256D from ChromiumOS repository.
This chip was added in `commit 0c38355c` by dlaurie@google.com
2019-03-17.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: I79d4ed48aa9126a8a6ce455a9564451346195b8f
Reviewed-on: https://review.coreboot.org/c/flashrom/+/35480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Change name of GD25LQ128 to GD25LQ128CD. This is an upstreaming of the
change from the chromium flashrom repo SHA
6c957d745f5d3dcadd1035734a5cf1b804bd0f2f (Also visible at
https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/1181175)
The rationale from that change was:
The GD25LQ128C part is EOL. It's replacement is GD25LQ128D, but
both chips identify in the same manner. Add GD25LQ128D to the name
of the part so that it doesn't confused people.
Making this name consistent will simplify further merging from the
chromium fork.
Change-Id: I57804f1a33170668e029a7b08ac050d9a3bd6dbb
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
The definition for the AT26DF321 has been commented out since it was
first added in 2008. The chip now appears to be obsolete, being marked
"obsolete" and unstocked at Digikey. It is also only referred to in
historical documents on the manufacturer's website (microchip.com).
To avoid further bitrot of this dead code, drop it.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: Ib30b3a16f25de5def508d90ec9375563b1d4d384
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
As per user `The_Raven Raven` on the mailing list. Since the added
values had some inconsistencies, the chips are marked as untested.
Change-Id: I6c26aafdca232110986334e85297d73d513600dc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Similar to W25Q256FV, but it supports the native 4BA page program
instruction (12h). Note that the variant with QE enabled by default
shares the device ID of the W25Q256FV.
Tested using a Raspberry Pi.
Change-Id: I76d7362777d364594d2a733d7e478741b0bef7c4
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/29305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Port the code from chromeos flashrom.
Tested using W25Q128JVSIM in SPI mode.
Change-Id: I38397a0c831407afa21cddca8485664576fce92c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/28910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The IS25WP064 was tested successfully by Simon Buhrow as reported on
2018-9-4. While we are at it, also add the 32Mbit version which shares
the datasheet (as does the already supported 128Mbit version).
Change-Id: Ie0887b4ae6e6465118a5dc2e20b784f783d161b8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Grabbed from mailing list, created by Simon Buhrow. Since no logs were
attached, the chip is marked as untested.
Change-Id: Idc26162fc5a5a429acef546b30b12d8b1f195e0a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Copy 'n paste support for Macronix MX25U51245G. I don't pretend to know
a whole lot about SPI FLASH so its mostly copied from other MX25U devices
and double checked a few bits and pieces against the datasheet.
I have tested basic probe, read, erase and write using layout files. I
tested both with 4MB@0x0000000 and 64K0@0x3f00000 (the later means I
have tested 4-byte addressing).
Change-Id: I2117fc205006088967f3d97644375d10db1791f1
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Reviewed-on: https://review.coreboot.org/26949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This is the low-voltage version of the AT25DF021. Tested with FT2232H
Mini Module
Change-Id: If4990e6856c8b77567ef4218459cf754b9c6bc57
Signed-off-by: Steffen Mauch <steffen.mauch@gmail.com>
Reviewed-on: https://review.coreboot.org/26856
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Same story as for 25Q80BW/EW, 25Q40EW has a new ID and the only known
chip with the old ID is the BW variant.
Change-Id: Ib610b0d6f3a5561b2ac3505ef15bdee8b0edae25
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/25462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This patch seems to have originally been from
https://patchwork.coreboot.org/patch/4126/ . The most recent version
seems to be in OpenEmbedded (commit 503a572) which added support for
16Mbit and 32Mbit variants.
The OpenEmbedded patch also makes changes to linux_spi.c to add some
debug prints which are omitted in this version.
From the original commit message:
Differences between SST26 and SST25:
1. The WREN instruction must be executed prior to WRSR [Section 5.31].
There is no EWSR.
2. Block protection bits are no longer in the status register. There
is a dedicated 144-bit register [Table 5-6]. The device is
write-protected by default. A Global Block-Protection Unlock
command unlocks the entire memory [Section 4.1].
Change-Id: Ib019bed8ce955049703eb3376c32a83ef607c219
Signed-off-by: Wei Hu <wei@aristanetworks.com>
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
Reviewed-on: https://review.coreboot.org/25962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The W25Q80BW appears to have been succeeded by the W25Q80EW which has a
different manufacturer ID but is otherwise similar. Consequently, W25Q80.W
no longer matches all chips in this family.
This patch makes the original entry specific to W25Q80BW.
Change-Id: I2980272c2691eb62a68056a7a4c308e9b4810347
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/25100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This introduces the Zettadevice manufacturer ID and adds support for the
ZD25D40 chip.
Based on PR20 from Github.
Change-Id: I0400b059ddacdf166d1b77f619becec3a250cece
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/23701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This adds support for W25P80/16/32 chips. Most notably these chips only
have two erase commands - one for 64KiB "sectors" and one for chip
erase.
Change-Id: Ie09ba8e28fee35c42e17ca05219dc673413de93b
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/23700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
IS25LP128 is the 3.3V variant, IS25WP128 is the 1.8V variant.
Tested read, erase, and write using Dediprog SF600 on each.
Change-Id: Ia1c7a9a950043c30b7525196e03ee394689e89a5
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/22784
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The (old) ST (now Micron) M25P05 does only support RES for identification.
Unfortunately, the vendor datasheet states the same ID as for the M25P10
(0x10) and thus flashrom has treated these two as evil twins in the past.
However, real hardware confirmed that the real ID of this chip is 0x05.
Change-Id: Idc75f8cb98e7ef0c47c4527cedcc4da3723bd779
Signed-off-by: Serge Vasilugin <vasilugin@yandex.ru>
Tested-by: Serge Vasilugin <vasilugin@yandex.ru>
Reviewed-on: https://review.coreboot.org/21920
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Only difference to its sibling W25Q128.V seems to be the supply voltage.
Change-Id: I34ce7f1bdd0d2fb1b065031e5a689bb16ffc70db
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
The earlier versions of the chip require 0x2AAA for probes thus split the
definitions and set them to untested to provoke reports.
Corresponding to flashrom svn r1922.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
