Not only does this violate the principle of least surprise, it also
caused one bug where -Ewv was specified and the flash ended up being
empty.
Support only one operation at a time. As a side benefit, this allows us
to clean up main() quite a bit.
Corresponding to flashrom svn r585.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Add timing info to some flash chips.
Corresponding to flashrom svn r584.
Signed-off-by: Mateusz Murawski <matowy@tlen.pl>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
There are multiple albatron pm266a boards which all share the same bios
image. This means that both the board enable and the subsystem ids are
exactly the same.
The board enable is the same as the epox EP-8K5A2, namely only raising
memw on the superio.
Corresponding to flashrom svn r581.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Mateusz Murawski <matowy@tlen.pl>
Some IDs were already in flash.h. EN25B05 EN25B10 EN25B20 EN25B40
EN25B80 EN25B16 EN25B32 EN25B64 EN25F40 EN25F80 EN25F16
EN25P* are supported as well, but they seem to be identical to EN25B.
Corresponding to flashrom svn r580.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Add chip_{read,write}n to the external flasher infrastructure which
read/write n bytes at once.
Fix a few places where the code used memcpy/memcmp although that is
strictly impossible with external flashers.
Place a FIXME in the layout.c code because usage is not totally clear
and needs to be fixed to support external flashers.
As a nice side benefit, we get a noticeable speedup for builtin flash
reading which is now a memcpy() of the full flash area instead of a
series of single-byte reads.
Corresponding to flashrom svn r579.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Urja Rannikko <urjaman@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Add external programmer delay functions so external programmers can
handle the delay on their own if needed.
Corresponding to flashrom svn r578.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Urja Rannikko <urjaman@gmail.com>
I finally found the machine (doesn't belong to me) where I originally tested
this board as non-working and I can confirm that all operations work fine now
(since the nForce2 patch in r548).
Corresponding to flashrom svn r571.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
This eliminates the conflicting delay requirements for old and new chips
with the same probing sequence.
Corresponding to flashrom svn r569.
Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Raises bits 0 and 2 on offset 0xE1 in the system control area of the
nvidia ck804 lpc.
Corresponding to flashrom svn r568.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Alexander Gordeev <lasaine@lvk.cs.msu.su>
Also do some random cleanups while I'm at it.
Corresponding to flashrom svn r567.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Also, add Atmel AT29C512 support.
Both are tested on hardware by Maciej Pijanka.
Corresponding to flashrom svn r566.
Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
- ASUS A8N-SLI (reported by Ryan McLean <pvtryan100@googlemail.com>)
- MSI/Medion MS-7255 (P4M890M) (reported by Jörg Schirottke <master@kanotix.com>)
Corresponding to flashrom svn r565.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Although the HT-1000 GPIOs are not SuperIO related, the share the same
index/data register access method.
Corresponding to flashrom svn r561.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
It doesn't make sense to probe for SPI chips on a LPC host, nor does it
make sense to probe for LPC chips on a Parallel host.
This change is backwards compatible, but adding host protocol info to
chipset init functions will speed up probing.
Once all chipset init functions are updated and the Winbond W29EE011 and
AMIC A49LF040A chip definitions are updated, the W29EE011 workaround can
be deleted as the W29/A49 conflict magically disappears.
Corresponding to flashrom svn r560.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested on real hardware and
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
The syntax is explained in the man page.
Example: flashrom -p dummy=lpc,fwh
Tested, works perfectly. ;-)
As a nice benefit, it allows easy testing of the "probe only compatible
flashes" patch.
Corresponding to flashrom svn r559.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
This is a fast way to test if a IT87xx board_enable() would work.
Corresponding to flashrom svn r557.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Harald Gutmann <harald.gutmann@gmx.net>
Right now, the annotation only differentiates between SPI and non-SPI.
Anyone who knows more about a specific flash chip should feel free to
update it.
The existing flashbus variable was abused to denote the SPI controller
type. Use an aptly named variable for that purpose.
Once this patch is merged, the chipset/programmer init functions can set
supported flash chip types and flashrom can automatically select only
matching probe/read/erase/write functions. A side benefit of that will
be the elimination of the Winbond W29EE011 vs. AMIC A49LF040A conflict.
Corresponding to flashrom svn r556.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Erase & write support wont be this easy - the chips need 12V Vpp
(needs a hardware hack or a supporting mb) and they have a very weird
layout and are old.
Corresponding to flashrom svn r555.
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
- Add explicit installation instructions in the README.
- Code cleanups, coding style fixes, drop dead code.
- Drop duplicate board listings from -L output (some boards were explicitly
recorded in boards_ok[] _and_ implicitly via the board-enables table.
- Add MS-xxxx numbers to MSI boards where we can find that info.
- Fix typo, "K8T Neo2" should have been "K8T Neo2-F" actually, at least
according to the comment of w83627thf_gpio4_4_raise_2e() which says
"Suited for: MSI K8T Neo2-F".
Corresponding to flashrom svn r554.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Marked as OK:
- ASUS M2V (reported by Henri Valta <henri.valta@kemi.fi>)
http://www.coreboot.org/pipermail/coreboot/2009-May/048674.html
- Jetway J7F4K1G5D-PB (reported by Kevin O'Connor <kevin@koconnor.net>)
- PC Engines Alix.3d3 (reported by Tobias Müller <Tobias_Mueller@twam.info>)
http://www.coreboot.org/pipermail/coreboot/2009-May/048549.html
- MSI K7N2 (reported by Maciej Pijanka <maciej.pijanka@gmail.com>)
http://www.coreboot.org/pipermail/coreboot/2009-May/048777.html
Marked as (so far) non-working:
- DFI 855GME-MGF (reported by Tobias Müller <Tobias_Mueller@twam.info>)
http://www.coreboot.org/pipermail/coreboot/2009-May/048549.html
- ASUS M3N78 Pro (reported by Piotr Esden-Tempski <esden@esden.net>)
As discussed on IRC this is an MCP78 chipset with SPI translation apparently
done in the southbridge, and we have no NVIDIA datasheets, of course. So the
situation for this board will probably not change anytime soon.
- MSI MS-6178 (reported by Uwe Hermann <uwe@hermann-uwe.de>)
I tested write/erase will not work on this board, so a write-enable is
needed. In _addition_, the board immediately powers off if you hot-unplug
the PLCC chip, so I guess there's some SMI interference.
- GIGABYTE GA-K8N-SLI (reported by Alexander Gordeev <lasaine@lvk.cs.msu.su>)
This is currently being discussed on the mailing list (see
http://www.coreboot.org/pipermail/coreboot/2009-May/048717.html) and it's
very likely that we'll be able to add a board-enable, so this board can be
maked as OK soonish.
Corresponding to flashrom svn r553.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
It currently even breaks -L output. We could of course fix that, but we already
use short/abbreviated names for other vendors (AMD, ST, SST, PMC) anyway.
Corresponding to flashrom svn r552.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Every chip besides SPI and w39v080fa uses id1/id2 as local variable
names to store ID responses from the flash chip. This eases grepping a
lot. As a bonus, it also frees up some names to be used as parameters.
Corresponding to flashrom svn r551.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
Corresponding to flashrom svn r550.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
RES is Read Electronic Signature (1 Byte, identical for different chips)
REMS is Read Electronic Manufacturer Signature (2 Bytes, mostly unique)
RDID is Read JEDEC ID (3 bytes, unique)
Of the chips which don't support RDID, a sizable portion supports REMS
which gives us both a manufacturer ID and a device ID. This is clearly
superior to having only a device ID (the RES case) which has multiple
documented collisions.
The RES/REMS problem is aggravated by inconsistent naming in vendor data
sheets. What's in a name? Considering that we have 1-byte IDs, 2-byte
IDs and 3+byte IDs with varying names but mostly consistent opcodes, it
makes sense to set our own standard about how the opcodes are called.
The best way forward would be to have the ICH SPI driver reprogram the
opcode menu on the fly if the opcode menu doesn't contain the requested
opcode and the opcode menu is not locked. Until that happens, this patch
improves detection accuracy by a factor of 256 for some chips.
Corresponding to flashrom svn r549.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested-by: Uwe Hermann
with the flash chip "SST SST25VF040.REMS".
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
While the other chipset enables for nvidia could potentially also work,
this one, by not touching other bits, seems like the safest solution.
Uwe tested this on his Asus A7N8X Deluxe, so hopefully the A7N8X-E
(reporter unknown) is now no longer an issue.
Corresponding to flashrom svn r548.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
We had duplicated code under different names and even open-coded some
functions in some places.
wbsio_read/regval -> sio_read wbsio_write/regwrite -> sio_write
wbsio_mask -> sio_mask
board_biostar_p4m80_m4 now uses existing IT87 functions.
Corresponding to flashrom svn r547.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Luc Verhaegen <libv@skynet.be>
Obvious typo due to inb/outb versus wbsio_ argument ordering confusion.
Corresponding to flashrom svn r546.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Thanks Christian Ruppert <spooky85@gmail.com> for testing on hardware.
(also: Fix a typo and some whitespace while I'm at it)
Corresponding to flashrom svn r545.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
- Update manpage, we now report supported boards via -L.
- Add some missing escaping for '-' characters in the manpage.
Corresponding to flashrom svn r543.
- Shorten some of the really long device names, so that -L output looks
nicer.
- Display a "table header" for all entries/columns in -L output.
- Make -L output tabular for all lists for better readability.
- Do not print "unknown XXXX SPI chip" entries in -L output.
- And random other cosmetics...
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
- ASUS P5B-Deluxe (reported by Andrew Paprocki)
- ASUS P6T Deluxe V2 (reported by Aldrik Dunbar)
- GIGABYTE GA-6ZMA (reported by Urja Rannikko)
- Intel EP80759 (reported by Stephan GUILLOUX)
- MSI MS-7345 (P35 Neo2-FIR) (reported by Onno)
- MSI MS-7168 (Orion) (reported by ubuntosaure)
- Supermicro H8QC8 (reported by Victor Zele)
Mark the following boards as 'known-bad' (they likely require a write-enable):
- Abit IS-10 (reported by deejkuba)
- ASUS P5B (reported by Henning Fleddermann)
- ASUS P5BV-M (reported by Bernhard M. Wiedemann)
- Boser HS-6637 (reported by Mark Robinson)
Also, mark the Winbond W39V040A as fully tested (report by ubuntosaure).
Corresponding to flashrom svn r542.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Thanks Heinz Wiesinger <HMWiesinger@liwjatan.at> for the report.
Corresponding to flashrom svn r541.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
- Mention that we'd like to have -V output for all operations
which were tested by the user.
- Mention that we'd like to know the exact mainboard vendor/name.
Corresponding to flashrom svn r540.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
I tested all operations on hardware.
Corresponding to flashrom svn r538.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
I tested identify, read, write, erase, verify successfully, HOWEVER,
this will only work (at least on my card) after de-soldering the
soldered-on PLCC32 one-time programmable (OTP) chip (Holtek HT27C010)
and soldering on a (re-)programmable flash ROM chip or a socket.
Example:
http://www.coreboot.org/File:Sii_controller1.jpghttp://www.coreboot.org/File:Sii_controller2.jpg
The OTP chip which came on my card does not react to the standard JEDEC
identify/read/write/erase commands anymore, so if all other such PCI0680
controllers which are around also have the same OTP chip (that's not
necessarily the case), they cannot be used as "external programmer" in
flashrom without the above mentioned modifications.
Corresponding to flashrom svn r536.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
