bb8e6f904b
flashchips: Add write-protect support for GD25LQ255E
...
datasheet: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20221129/DS-00562-GD25LQ255E-Rev1.1.pdf
BUG=b:311336475
TEST=Verified on karis
w/o this patch:
$ flashrom_tester --flashrom_binary ./flashrom internal Lock_top_quad
--> Failed
w/ this patch:
$ flashrom_tester --flashrom_binary ./flashrom internal Lock_top_quad
--> Pass
This lock_top_quad test did(copied from partial_lock_test()):
* Disable hardware WP so we can modify the protected range.
* Then enable software WP so the range is enforced and enable
hardware WP so that flashrom does not disable software WP during the
operation.
* Check that we cannot write to the protected region.
* Check that we can write to the non protected region.
Change-Id: I1425e931433c00caceaabc6037a79099d6d5eac5
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/79460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nikolai Artemiev <nartemiev@google.com >
Reviewed-by: Hsuan-ting Chen <roccochen@google.com >
2024-01-05 03:55:57 +00:00
6f3339fda6
flashchips: Add GD25LQ255E
...
datasheet: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20221129/DS-00562-GD25LQ255E-Rev1.1.pdf
BUG=b:311336475
TEST=(1) flashrom -p internal -r /tmp/bios.bin, get "SUCCESS" result
(2) flashrom -p internal -w /tmp/bios.bin, get "SUCCESS" result
(3) flashrom -i RW_MRC_CACHE -E, get "SUCCESS" result
Change-Id: I0d780255ed6772f4aa406584acf071a7ddd6da47
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/79088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Hsuan-ting Chen <roccochen@google.com >
Reviewed-by: Nikolai Artemiev <nartemiev@google.com >
2024-01-05 03:54:45 +00:00
abd9a1e9e8
flashchips: Split GD25Q127C/GD25Q128C and add GD25Q128E
...
Q127C and Q128C are not the same. Q127C doesn't support QPI but Q128C
does. So we need to split the existing GD25Q127C/GD25Q128C into two
separated entries. We also introduce the new flashchip Q128E and merge
it into Q127C.
Datasheets:
Q128E: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00480-GD25Q128E-Rev1.2.pdf
Q127C: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00220-GD25Q127C-Rev2.3.pdf
Q128C: https://www.endrich.com/sixcms/media.php/2/GD25Q128C-Rev2.pdf
Q128E and Q127C/Q128C have compatible main functions, their differences
are:
* Q128E uses 55 nm process, while Q127C/Q128C use 65nm
* Q128E/Q127C does not support QPI
* Q128E/Q127C have OTP: 3072B, while Q128C are 1536B
* Q128E's fast read clock frequency is 133MHz, while Q127C/Q128C are
104MHZ
So we decided to merge Q128E into Q127C.
We also tested that Q128E could pass flashrom_tester while probing it as
127C/128C, so the main functionalities are compatible.
Change the chip name from GD25Q127C/GD25Q128C to two entries
GD25Q127C/GD25Q128E and GD25Q128C to make it more accurate.
Chip revision history:
- The 'GD25Q127C/GD25Q128C' definition was added in
`commit e0c7abf219b81ad049d09a4671ebc9196153d308` as 'GD25Q128C' and
later renamed to 'GD25Q127C/GD25Q128C'
BUG=b:304863141, b:293545382
BRANCH=none
TEST=flashrom_tester with flashrom binary could pass with Q128E,
which contains probe, read, write, erase, and write protect
Signed-off-by: Hsuan Ting Chen <roccochen@google.com >
Change-Id: I3300671b1cf74b3ea0469b9c5a833489ab4914f5
Reviewed-on: https://review.coreboot.org/c/flashrom/+/78348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2023-11-19 23:23:46 +00:00
41cb46672e
flashchips: change print lock status funcs for Winbond chips
...
Decode status register bits for user friendly output.
Signed-off-by: Alexander Goncharov <chat@joursoir.net >
Change-Id: I5066863b514825aee0dffe496492514ac99b6e49
Reviewed-on: https://review.coreboot.org/c/flashrom/+/75877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nikolai Artemiev <nartemiev@google.com >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2023-11-18 20:52:33 +00:00
8a7f8ade46
spi25_statusreg: rename amic_a25l032 print to a generic name
...
Other chips (at least Winbond) will benefit from this change.
Also, drop the FIXME comment, as it can be misleading. The
"pretty print" functions should only display values from the
Status Register, so using an inappropriate function might only
confuse user.
Signed-off-by: Alexander Goncharov <chat@joursoir.net >
Change-Id: I7169a2312698343e1065cdca91a3985e00cb3804
Reviewed-on: https://review.coreboot.org/c/flashrom/+/78874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
Reviewed-by: Nikolai Artemiev <nartemiev@google.com >
2023-11-18 20:52:05 +00:00
52b794ff26
flashchips: Add Puya P25Q21H/11H/06H
...
Datasheet:
https://semic-boutique.com/wp-content/uploads/2016/05/P25Q21H-SSH-IT.pdf
Tested P25Q21H read, write and probe with CH341a.
Signed-off-by: Nita Vesa <werecatf@outlook.com >
Change-Id: Idd43145c72607837cb7afa1b007e68eb8e63ebd9
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58134
Reviewed-by: Alexander Goncharov <chat@joursoir.net >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-11-05 23:56:33 +00:00
fba29da188
flashchips: Mark FM25F01 as tested for read/write/probe/erase
...
As reported on the mailing list:
https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/JSCQPE3XN3WV6SN4SQH3YNGK2TUKGIZF/
Change-Id: Ibb65a4cb3345eb67c049aa4d8bfd3260f4bf96db
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/78397
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-10-20 06:34:44 +00:00
47d3dcd4c9
flashchips: Add write-protect support for MXIC MX25U25643G
...
The MX25U25643G has a WPSEL bit in the security register, but the MX25U25635F does not.
Therefore, take them apart.
We have tested --wp-enable, --wp-disable, --wp-list and --wp-range
commands for write-protect feature.
The MX25U25643G has been tested by ch341a programmer : read, write,
erase and wp.
MX25U25643G datasheet is available at the following URL:
https://www.mxic.com.tw/en-us/products/NOR-Flash/Serial-NOR-Flash/Pages/spec.aspx?p=MX25U25643G&m=Serial%20NOR%20Flash&n=PM2832
MX25U25635F datasheet is available at the following URL:
https://www.macronix.com/en-us/products/NOR-Flash/Serial-NOR-Flash/Pages/spec.aspx?p=MX25U25635F&m=Serial%20NOR%20Flash&n=PM1712
Change-Id: I43de9ed123b9736c04d070754bcf9c32be5697ad
Signed-off-by: rogeryou <rogeryou@mxic.com.cn >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/78142
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-10-13 00:56:49 +00:00
6f14eadfac
flashchips: Mark Atmel AT29C010A chip as tested for write operation
...
As reported on the mailing list in
https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/4BU4LPRIBXCPOFI6MUG2CHOU5YBLUNN7/
Change-Id: I267ed5583e8a9bad0b34b12d73ab2928d65144eb
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/78069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
2023-10-07 04:42:11 +00:00
5234c57e33
flashchips: add WP features for W25X* analogous to tested W25X20
...
These chips were not tested physically, just added since they are very similar to
just added and tested W25X20.
However basic logic test were done via running
--wp-list with dummy emulating those IDs
While there are per-chip datasheets like
https://www.winbond.com/resource-files/W25X05CL_G%2008012019.pdf
the combined datasheets that shows differences between WP modes
of different chips are more useful:
https://www.winbond.com/resource-files/w25x10a-20a-40a-80a%20revf%20080709.pdf
https://media.digikey.com/pdf/data%20sheets/winbond%20pdfs/w25x16,16a,32,64.pdf
Signed-off-by: Vasily Galkin <galkin-vv@ya.ru >
Change-Id: Ie69660a6f69e3cac31c5565792f401e69d43f8b8
Reviewed-on: https://review.coreboot.org/c/flashrom/+/77531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nikolai Artemiev <nartemiev@google.com >
2023-09-30 00:20:58 +00:00
9ccbf1cf43
flashchips: Add support for XMC XM25QH80B
...
XM25QH80B has the same ID as M45PE80, but has more features.
Tested with CH341A.
Change-Id: Ib51225426d8d1a381d45af3574e5ba2bf02837aa
Signed-off-by: Sungbo Eo <mans0n@gorani.run >
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63516
Reviewed-by: Nikolai Artemiev <nartemiev@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-09-22 05:32:40 +00:00
ebda447ad9
flashchips: Add support for MXIC MX25U25643G
...
It is similar to the MX25U25635F and shares its RDID.
Tested by ch341a programmer : read, write and erase.
Datasheet is available at the following URL:
https://www.mxic.com.tw/en-us/products/NOR-Flash/Serial-NOR-Flash/Pages/spec.aspx?p=MX25U25643G&m=Serial%20NOR%20Flash&n=PM2832
Change-Id: Ie04a5e2325aab94bffb276675be3fa4a88c6e134
Signed-off-by: xianzheng <xianzheng@mxic.com.cn >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/76853
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-09-17 09:06:17 +00:00
aa468cf0bd
flashchips: add definition of the XT25F02E SPI NOR flash
...
This adds definition of the XT25F02E 2MBit SPI NOR Flash
from XTX Technology Limited.
Tested (Probe, Erase, Write, Read) with a VL805 USB3.0 bridge.
Datasheet:
https://datasheet.lcsc.com/lcsc/2006091008_XTX-XT25F02EDTIGT_C596313.pdf
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com >
Change-Id: I295633c448c05520e4a6aa09c08bd7c9f2346d54
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/50263
Reviewed-by: Peter Marheine <pmarheine@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-09-16 08:41:46 +00:00
7617467544
flashchips: Add WP features for Winbond W25X20
...
WP-related registers list from official datasheet
https://www.winbond.com/resource-files/w25x20cl_revf%2020150806.pdf
Commandline options tested with ft2232_spi-based "Tigard" programmer:
wp-disable wp-enable wp-list wp-status wp-range=0,0 wp-range=0,0x00040000
Signed-off-by: Vasily Galkin <galkin-vv@ya.ru >
Change-Id: I82c0cc52ca2a78d27f513234cc12d3e09d8905a5
Reviewed-on: https://review.coreboot.org/c/flashrom/+/77530
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-09-03 08:30:21 +00:00
86907148c6
flashchips.c: Add support for IS25WQ040
...
Based on https://github.com/flashrom/flashrom/pull/204
squashed with fixes of IS25WQ040 size: it is 4Mbits, not 4MBytes, see
https://www.issi.com/WW/pdf/25WQ020-040.pdf
Tested read, write and erase with ft2232_spi-based "Tigard" programmer.
Change-Id: I072c6b94d7931637d1c2721c3316205f2d57320e
Signed-off-by: Roman Stingler <roman.stingler@gmail.com >
Signed-off-by: Vasily Galkin <galkin-vv@ya.ru >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58179
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-30 08:53:40 +00:00
2bfc85b2a6
flashchips: add Macronix MX25L3255E
...
Tested using the linux_spi programmer on a Raspberry Pi.
Datasheet:
https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L3255E.pdf
Signed-off-by: Joseph C. Lehner <joseph.c.lehner@gmail.com >
Change-Id: I65968771e22e6b823d2d6192c33f5b0cba25d5b9
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/57410
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-23 09:43:05 +00:00
8a3db802ea
flashchips: Add ISSI IS25LQ016
...
Datasheet: http://www.issi.com/WW/pdf/25LQ016.pdf
Tested all four PREW functions with a FT2232H.
Change-Id: I02f19767b8a60fb2d37adab34894b6edb6ac4494
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nikolai Artemiev <nartemiev@google.com >
2023-08-15 06:11:21 +00:00
91aa2d8526
flashchips: Add XTX XT25F64B
...
Datasheet:
http://file2.dzsc.com/product/19/06/22/216185_132959081.pdf
Tested probe, read, erase and write with CH341a.
Signed-off-by: Nita Vesa <werecatf@outlook.com >
Change-Id: I369db9ccfd5319d28424d10f77aab49ec73a8836
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Peter Marheine <pmarheine@chromium.org >
2023-07-17 01:12:53 +00:00
af8c203436
flashchips: add support for MX77L25650F chip
...
Add initial support for Macronix MX77L25650F. Can read, write and erase
the chip.
Change-Id: Iaea5485f8b59b8538dc47beada2c308376ea027c
Signed-off-by: Artur Kowalski <artur.kowalski@3mdeb.com >
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com >
Signed-off-by: ServError <admin@serverror.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/68557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2023-07-12 07:53:07 +00:00
aac723f184
flashchips.c: Adding support for ISSI IS25WP020/40/80
...
This patch added support for IS25WP020, IS25WP040, and IS25WP080
SPI flash chips. The datasheet for these chips can be
found at: https://www.issi.com/WW/pdf/25WP016_080_040_020.pdf
Tested read, write, and erase functions on IS25WP080.
Test log:
Write: https://paste.flashrom.org/view.php?id=3698
Write test 2: https://paste.flashrom.org/view.php?id=3699
Erase: https://paste.flashrom.org/view.php?id=3700
Change-Id: I8a786de5cf9ffefb2d57f89bbab71e289b5c2b28
Signed-off-by: Ao Zhong <hacc1225@gmail.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/75830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2023-07-12 07:42:36 +00:00
b66f4766b5
flashchips: add support for MX25V16066/KH25V16066
...
Change-Id: Ic5f0548f023fcd09a970148586497e00414ad1ae
Signed-off-by: Joseph Goh <josephgoh7@gmail.com >
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/68278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2023-06-30 07:59:44 +00:00
1ee04cd5ac
flashchips: Add support for XMC XM25QH128A
...
Tested: read, write and erase.
Chip (and datasheet) have recenty been removed from XMC's website
but can still be retrieved through web archive:
https://web.archive.org/web/20221122191724/https://www.semiee.com/file/XMC/XMC-XM25QH128A.pdf
Signed-off-by: Stijn Segers <foss@volatilesystems.org >
Change-Id: Iced40403c6694a55fd648ea2785cdcba21712234
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/69309
Reviewed-by: Nikolai Artemiev <nartemiev@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2023-06-21 11:59:48 +00:00
4652df95f1
flashchips: add support for ISSI IS25LP016
...
I took the original patch from Ondrej Hennel [1] and applied the
requested changes. Reading, erasing and writing works.
[1] https://patchwork.ozlabs.org/project/flashrom/list/?series=261647
Change-Id: Iffd7c4284d4d96b30a94f5dee882b5403fdfc183
Signed-off-by: Mario Kicherer <dev@kicherer.org >
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/68295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nikolai Artemiev <nartemiev@google.com >
2023-06-16 01:16:47 +00:00
4325bb5b1f
flashchips: Add AT25DF011
...
Tested read/write/erase/probe operations with a ch341a_spi programmer.
Datasheet is available at https://www.mouser.de/datasheet/2/590/DS-AT25DF011_032-1098683.pdf
Signed-off-by: Hanno Heinrichs <hanno.heinrichs@rwth-aachen.de >
Change-Id: I5a2141f1380e864c843d6a3008fdb02dc1b75131
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/51048
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Reviewed-by: Nikolai Artemiev <nartemiev@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-06-16 01:03:10 +00:00
5dabb7c423
flashchips: Mark S25FL128L as tested for probe, read, write, erase
...
As reported on the mailing list:
https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/3CC54GMEBXYVOXBJ7J5NZ5R4SQ42ZOXC/
Change-Id: I0700d3e4f684db096fea63eb9bc5add44e246758
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/75604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
2023-06-11 09:32:00 +00:00
1c22de20ea
flashchips: Add support for IS25WP016
...
Tested reading, writing and erasing using `linux_spi` programmer
on Raspberry Pi CM4.
Datasheet: https://web.archive.org/web/20221129211027/https://www.issi.com/WW/pdf/25LP-WP016D.pdf
Change-Id: I2b8caea229ffda72f1b04183c31715faccb64ad5
Signed-off-by: Alex Mikhalev <alex@corvus-robotics.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/70140
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-06-08 08:02:46 +00:00
104503375d
flashchips: Add support for Boya BY25D80A
...
Read tested on Raspberry Pico with pico-serprog
Change-Id: I586f3455d925132bbda3fccdad00f0b1e22c2ea7
Signed-off-by: Piotr Halama <skrzynka@halamix2.pl >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/73513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Peter Marheine <pmarheine@chromium.org >
2023-06-08 07:41:45 +00:00
9b3a70158c
flashchips.c: Add write protect support for W25Q16.V
...
Enable WRSR2 feature flag and define reg_bits and decode_range for
W25Q16.V to enable write protect support.
Based on W25Q16DV, Revision: 1, Release: Nov 18 2014 datasheet
TEST=flashrom --wp-{enable,disable,range,list,status}
Change-Id: I6c0b35f82b47a1169bccfd08222e9e3b3be30d75
Signed-off-by: Khoa Hoang <admin@khoahoang.com >
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/67713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com >
2023-06-05 07:52:44 +00:00
21901c11e7
tree/: Case write_granularity enum values
...
Change-Id: Ic8c655225abe477c1b618dc685b743e691c16ebd
Signed-off-by: Edward O'Callaghan <quasisec@google.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/74165
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-04-06 05:15:03 +00:00
9a2284503e
flashchips: Add Macronix MX25V1635F support
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See https://www.mxic.com.tw/Lists/Datasheet/Attachments/8662/MX25V1635F,%202.5V,%2016Mb,%20v1.4.pdf .
I've tested this patch with the MX25V1635F I have here, using serprog
and ftdi by (re)writing a few images to the flash and seeing if changes
were stored correctly. This also included erasing and rewriting the
memory with completely different data, so erase is tested, too.
Change-Id: I58ddaaa96ef410d50dde3aaa20376c5bbf0f370b
Signed-off-by: PoroCYon <p@pcy.be >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/73824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2023-03-26 09:04:07 +00:00
c6ba433b3b
flashchips: Add Macronix MX25V8035F support
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See https://www.macronix.com/Lists/Datasheet/Attachments/8405/MX25V8035F,%202.5V,%208Mb,%20v1.0.pdf .
I've only tested this patch with the MX25V1635F I have here, though
other chips in the series exist as well. Tested using serprog and ftdi
by writing a few images to the flash and seeing if changes were stored
correctly.
Change-Id: Ic5be2da4cfa2a2ff044a519bb6f367f21c15e4b8
Signed-off-by: PoroCYon <p@pcy.be >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/73823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2023-03-26 09:03:46 +00:00
5b8b6995a7
flashchips: Add Macronix MX25V4035F support
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See https://www.macronix.com/Lists/Datasheet/Attachments/8670/MX25V4035F,%202.5V,%204Mb,%20v1.2.pdf .
I've only tested this patch with the MX25V1635F I have here, though
other chips in the series exist as well. Tested using serprog and ftdi
by writing a few images to the flash and seeing if changes were stored
correctly.
Change-Id: I8b26926c354b840ca7b14b4c5cb000e3c02f5137
Signed-off-by: PoroCYon <p@pcy.be >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/73582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2023-03-26 09:02:53 +00:00
921be8f9ce
flashchips: Mark AM29LV040B as write-tested
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Reported by Alex Perez on the mailing list, write operation done
successfully with satasii programmer.
https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/67OX4CSBGWAGMNGEOATBJGFJCKFD64SU/
Change-Id: I8a42f8214b09c455a10a1f1e9e69feaeca2c62a1
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/73429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Thomas Heijligen <src@posteo.de >
2023-03-06 12:43:51 +00:00
002f1ee9da
flashchips: Mark XMC XM25QH64C as TEST_OK_PREW
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As reported on the mailing list[0] this flashchip was successfully
probed, read, erased and written with a ch341a programmer.
[0] https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/message/SMIHEXHZBSCGE2Y2EG75XQHWSKEQ3PP6
Change-Id: Ifca84d9a44bb20091293356f5b1643de41220b64
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/73363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2023-03-06 12:43:07 +00:00
5043f8f8c3
flashchips: Mark XMC XM25QH256C as TEST_OK_PR
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As reported on the mailing list[0] this flashchip was successfully
probed and read with a ch341a programmer.
[0] https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/message/BFBKAJKURZHYQ6OTV3UAA7V5O2ZSJWGN
Change-Id: I68d0315f7b29f27ac84374ea7cc69dca207bbacb
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/73362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2023-03-06 12:43:00 +00:00
ae07072e0a
flashchips.c: Add reg_bits for W25Q256JW_DTR
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Add reg_bits for W25Q256JW_DTR as per the datasheet.
BUG=b:263410331
TEST=Verified on google/rex.
w/o this patch:
Failed to get WP status: WP operations are not implemented for this chip
w/ this patch:
flashrom -p internal --wp-range 0x0,0x2000000
flashrom -p internal --wp-enable
flashrom -p internal --wp-status
flashrom -p internal -E <---- failed to erase the flash as WP (which is
expected)
Signed-off-by: Kapil Porwal <kapilporwal@google.com >
Change-Id: I8ac23f706d4293a7d7d11ad6b2f62526fb075367
Reviewed-on: https://review.coreboot.org/c/flashrom/+/70549
Reviewed-by: Subrata Banik <subratabanik@google.com >
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-02-21 07:00:46 +00:00
d18c099cac
flashchips: Remove FEATURE_4BA_WREN for MT25QL128 and mark as tested
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Using both a Dediprog SF100 and a Bus Pirate, read and erase works
correctly on a MT25QL128 but writes were failing to take effect.
Currently, the entry in flashchips.c indicates that this device supports
4-byte addressing. Micron's datasheet indicates that it does not.
After removing FEATURE_4BA_WREN from feature_bits, both SF100 and
Bus Pirate were able to successfully read, erase, and write a
MT25QL128 so also marking as tested.
Change-Id: I6341456c722840a413bd2c51fe9a78bbda5cdbab
Signed-off-by: Rick Altherr <kc8apf@kc8apf.net >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/71206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2023-01-15 10:28:19 +00:00
ed1126fc42
flashchips.c: Mark W25Q128.V WP as tested
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BUG=b:258755442
TEST=`-p internal --wp-status`.
Change-Id: Ifbd5ee76f2087764ab8841ca96de6990cb31260d
Signed-off-by: Edward O'Callaghan <quasisec@google.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/70866
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-12-19 22:39:33 +00:00
9394b84c00
flashchips: Add WP settings for Flash Chip W25Q512NW
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This patch adds WP register bits and decode range for Flash
Chip `W25Q512NW`.
TEST=Able to flash AP FW, wp-enable/disable on Google/rex device
which has flash chip `W25Q512NW`.
Signed-off-by: Subrata Banik <subratabanik@google.com >
Change-Id: Ic5148f71404466dcf7772e3eb6e1800eb8666696
Reviewed-on: https://review.coreboot.org/c/flashrom/+/67827
Reviewed-by: Kapil Porwal <kapilporwal@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Nikolai Artemiev <nartemiev@google.com >
2022-12-16 03:19:43 +00:00
c936ce4688
flashchips.c: Indent definition of W25Q512NW-IM properly
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Signed-off-by: Felix Singer <felixsinger@posteo.net >
Change-Id: Icfd2a49383da0f8f0a4e3295aba81ce1d200652c
Reviewed-on: https://review.coreboot.org/c/flashrom/+/68151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
2022-12-16 03:19:37 +00:00
7f3c3f5c48
flashchips.c: remove WREN from GD25Q256D enter 4BA sequence
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As noted in a comment on
`commit 86fc9cf7ab221bc54ef6f10252e296fc2d7a22d2`, the GD25Q256D
datasheet indicates that the chip does not require a WREN command to
enter 4BA mode.
Testing has confirmed that a WREN command is not required, so change the
flashchip feature flags from FEATURE_4BA_WREN to FEATURE_4BA.
Ticket: https://ticket.coreboot.org/issues/356
BUG=none
BRANCH=none
TEST=read/write/erase/verify GD25Q256D flash with FT2232H programmer
TEST=called spi_enter_exit_4ba(true), dumped registers, checked ADS=1.
Change-Id: I96e48933f33c52c0d10a0d4cb7f7e07c1fceab99
Signed-off-by: Nikolai Artemiev <nartemiev@google.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/70342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2022-12-08 23:12:55 +00:00
f27e19a331
flashchips.c: Add 4BA write to XM25Qx256C
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Flash chips XM25QH256C and XM25QU256C support the 4-byte program
command (0x12) according to their datasheets, but the feature flag is
not enabled in flashchips.c, so enable it to allow this feature to be
used.
TICKET: https://ticket.coreboot.org/issues/371
BUG=b:259493706
TEST=build
Change-Id: I96c80762fcda2af6028c7a53d8c545b0c6565cbd
Signed-off-by: Liam Flaherty <liamflaherty@chromium.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/69713
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2022-12-01 03:27:23 +00:00
8d0816faa5
tree/: Convert flashchips db to use indirection for printlock
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This paves the way to allow for the conversion of flashchip printlock
func ptr to enumerate values. This change should be a NOP.
TEST=`diff -u <(objdump -D flashchips.o_bk) <(objdump -D flashchips.o)`.
Change-Id: Icff868d9454e9b0a059a736457bb562430436033
Signed-off-by: Nikolai Artemiev <nartemiev@google.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/69844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
2022-11-23 06:18:51 +00:00
487d0408ff
tree/: Convert flashchips db to use indirection for unlock
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This paves the way to allow for the conversion of flashchip unlock
func ptr to enumerate values. This change should be a NOP.
TEST=`diff -u <(objdump -D flashchips.o_bk) <(objdump -D flashchips.o)`.
Change-Id: I3ed51142cd22becc8286959f5504565158fa2de0
Signed-off-by: Edward O'Callaghan <quasisec@google.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/69843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
2022-11-23 06:18:21 +00:00
56ebda5341
flashchips.c: enable WP for 7 entries of MX chips
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These weren't split:
* MX25L3206E/MX25L3208E
Tested: https://github.com/Dasharo/flashrom/pull/8
* MX25L6405
* MX25L6405D
* MX25L6406E/MX25L6408E
Tested: https://github.com/Dasharo/flashrom/pull/8
MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E/MX25L6473F was split into:
* MX25L6436E/MX25L6445E/MX25L6465E
- security register
- WPS
- tested: https://github.com/Dasharo/flashrom/pull/8
* MX25L6473E
- security register
- OTP TB bit in CONFIG/STATUS2 (0x15 opcode)
- WPS
* MX25L6473F
- NO security register
- OTP TB bit in CONFIG/STATUS2 (0x15 opcode)
- NO WPS
Change-Id: Ib3db9d39ffacd3e9e44de92c6cfb6c3ecc8615bd
Tested-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com >
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/66216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2022-11-19 07:14:53 +00:00
f6b486da14
flashchips.c: enable WP for MT25QL512, N25Q0{32,64}..{1,3}E
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Change-Id: Ib0f3cb9516cea7bb678842a358a82099221e1ed9
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/66215
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-11-19 07:14:25 +00:00
1428ca25d2
flashchips.c: enable WP for W25Q32.V, W25Q32.W and W25Q32JW...M
...
Split chips:
* W25Q32.V -> W25Q32BV/W25Q32CV/W25Q32DV, W25Q32FV and W25Q32JV
* W25Q32.W -> W25Q32BW/W25Q32CW/W25Q32DW, W25Q32FW and W25Q32JW...Q
Change-Id: Id259c27dfa6c681bbadc73b3bd7559ad6a5865f4
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/66214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2022-11-19 07:13:00 +00:00
d899d98859
flashchips.c: enable WP for EN25QH32 and EN25QH64
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Split chips:
* EN25QH32 -> EN25QH32 and EN25QH32B
* EN25QH64 -> EN25QH64 and EN25QH64A
Unlike older revisions both newly added EN25QH32B and EN25QH64A support
half block (32KiB) erase operation via 0x52 opcode.
Change-Id: I759f0119346235ce0bddc78cde9c461495990c25
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/66213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
2022-11-19 07:12:07 +00:00
3c44e12a28
tree/: Convert flashchips db to use indirection for erase_block
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This paves the way to allow for the conversion of flashchip erase_block
func ptr to enumerate values. This change should be a NOP.
TEST=`diff -u <(objdump -D flashchips.o_bk) <(objdump -D flashchips.o)`.
Change-Id: I122295ec9add0fe0efd27273c9725e5d64f6dbe2
Signed-off-by: Edward O'Callaghan <quasisec@google.com >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/69131
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-11-11 07:40:02 +00:00
2f0e49c2ab
flashchips: Add write protect bits to W25Q64JW...M
...
https://www.winbond.com/hq/support/documentation/levelOne.jsp?__locale=en&DocNo=DA00-W25Q64JW
BUG=b:245996788
BRANCH=None
TEST=None
Change-Id: Idf2289b7c90724ececc122d2a05c7cae3af2cf62
Signed-off-by: Evan Benn <evanbenn@chromium.org >
Reviewed-on: https://review.coreboot.org/c/flashrom/+/67719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org >
Reviewed-by: Nikolai Artemiev <nartemiev@google.com >
2022-11-10 05:13:21 +00:00
