Marked as OK:
- ASUS M2V (reported by Henri Valta <henri.valta@kemi.fi>)
http://www.coreboot.org/pipermail/coreboot/2009-May/048674.html
- Jetway J7F4K1G5D-PB (reported by Kevin O'Connor <kevin@koconnor.net>)
- PC Engines Alix.3d3 (reported by Tobias Müller <Tobias_Mueller@twam.info>)
http://www.coreboot.org/pipermail/coreboot/2009-May/048549.html
- MSI K7N2 (reported by Maciej Pijanka <maciej.pijanka@gmail.com>)
http://www.coreboot.org/pipermail/coreboot/2009-May/048777.html
Marked as (so far) non-working:
- DFI 855GME-MGF (reported by Tobias Müller <Tobias_Mueller@twam.info>)
http://www.coreboot.org/pipermail/coreboot/2009-May/048549.html
- ASUS M3N78 Pro (reported by Piotr Esden-Tempski <esden@esden.net>)
As discussed on IRC this is an MCP78 chipset with SPI translation apparently
done in the southbridge, and we have no NVIDIA datasheets, of course. So the
situation for this board will probably not change anytime soon.
- MSI MS-6178 (reported by Uwe Hermann <uwe@hermann-uwe.de>)
I tested write/erase will not work on this board, so a write-enable is
needed. In _addition_, the board immediately powers off if you hot-unplug
the PLCC chip, so I guess there's some SMI interference.
- GIGABYTE GA-K8N-SLI (reported by Alexander Gordeev <lasaine@lvk.cs.msu.su>)
This is currently being discussed on the mailing list (see
http://www.coreboot.org/pipermail/coreboot/2009-May/048717.html) and it's
very likely that we'll be able to add a board-enable, so this board can be
maked as OK soonish.
Corresponding to flashrom svn r553.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
It currently even breaks -L output. We could of course fix that, but we already
use short/abbreviated names for other vendors (AMD, ST, SST, PMC) anyway.
Corresponding to flashrom svn r552.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Every chip besides SPI and w39v080fa uses id1/id2 as local variable
names to store ID responses from the flash chip. This eases grepping a
lot. As a bonus, it also frees up some names to be used as parameters.
Corresponding to flashrom svn r551.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
Corresponding to flashrom svn r550.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
RES is Read Electronic Signature (1 Byte, identical for different chips)
REMS is Read Electronic Manufacturer Signature (2 Bytes, mostly unique)
RDID is Read JEDEC ID (3 bytes, unique)
Of the chips which don't support RDID, a sizable portion supports REMS
which gives us both a manufacturer ID and a device ID. This is clearly
superior to having only a device ID (the RES case) which has multiple
documented collisions.
The RES/REMS problem is aggravated by inconsistent naming in vendor data
sheets. What's in a name? Considering that we have 1-byte IDs, 2-byte
IDs and 3+byte IDs with varying names but mostly consistent opcodes, it
makes sense to set our own standard about how the opcodes are called.
The best way forward would be to have the ICH SPI driver reprogram the
opcode menu on the fly if the opcode menu doesn't contain the requested
opcode and the opcode menu is not locked. Until that happens, this patch
improves detection accuracy by a factor of 256 for some chips.
Corresponding to flashrom svn r549.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested-by: Uwe Hermann
with the flash chip "SST SST25VF040.REMS".
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
While the other chipset enables for nvidia could potentially also work,
this one, by not touching other bits, seems like the safest solution.
Uwe tested this on his Asus A7N8X Deluxe, so hopefully the A7N8X-E
(reporter unknown) is now no longer an issue.
Corresponding to flashrom svn r548.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
We had duplicated code under different names and even open-coded some
functions in some places.
wbsio_read/regval -> sio_read wbsio_write/regwrite -> sio_write
wbsio_mask -> sio_mask
board_biostar_p4m80_m4 now uses existing IT87 functions.
Corresponding to flashrom svn r547.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Luc Verhaegen <libv@skynet.be>
Obvious typo due to inb/outb versus wbsio_ argument ordering confusion.
Corresponding to flashrom svn r546.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Thanks Christian Ruppert <spooky85@gmail.com> for testing on hardware.
(also: Fix a typo and some whitespace while I'm at it)
Corresponding to flashrom svn r545.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
- Update manpage, we now report supported boards via -L.
- Add some missing escaping for '-' characters in the manpage.
Corresponding to flashrom svn r543.
- Shorten some of the really long device names, so that -L output looks
nicer.
- Display a "table header" for all entries/columns in -L output.
- Make -L output tabular for all lists for better readability.
- Do not print "unknown XXXX SPI chip" entries in -L output.
- And random other cosmetics...
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
- ASUS P5B-Deluxe (reported by Andrew Paprocki)
- ASUS P6T Deluxe V2 (reported by Aldrik Dunbar)
- GIGABYTE GA-6ZMA (reported by Urja Rannikko)
- Intel EP80759 (reported by Stephan GUILLOUX)
- MSI MS-7345 (P35 Neo2-FIR) (reported by Onno)
- MSI MS-7168 (Orion) (reported by ubuntosaure)
- Supermicro H8QC8 (reported by Victor Zele)
Mark the following boards as 'known-bad' (they likely require a write-enable):
- Abit IS-10 (reported by deejkuba)
- ASUS P5B (reported by Henning Fleddermann)
- ASUS P5BV-M (reported by Bernhard M. Wiedemann)
- Boser HS-6637 (reported by Mark Robinson)
Also, mark the Winbond W39V040A as fully tested (report by ubuntosaure).
Corresponding to flashrom svn r542.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Thanks Heinz Wiesinger <HMWiesinger@liwjatan.at> for the report.
Corresponding to flashrom svn r541.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
- Mention that we'd like to have -V output for all operations
which were tested by the user.
- Mention that we'd like to know the exact mainboard vendor/name.
Corresponding to flashrom svn r540.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
I tested all operations on hardware.
Corresponding to flashrom svn r538.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
I tested identify, read, write, erase, verify successfully, HOWEVER,
this will only work (at least on my card) after de-soldering the
soldered-on PLCC32 one-time programmable (OTP) chip (Holtek HT27C010)
and soldering on a (re-)programmable flash ROM chip or a socket.
Example:
http://www.coreboot.org/File:Sii_controller1.jpghttp://www.coreboot.org/File:Sii_controller2.jpg
The OTP chip which came on my card does not react to the standard JEDEC
identify/read/write/erase commands anymore, so if all other such PCI0680
controllers which are around also have the same OTP chip (that's not
necessarily the case), they cannot be used as "external programmer" in
flashrom without the above mentioned modifications.
Corresponding to flashrom svn r536.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Thanks Michael Heimann for reporting.
The board was misidentified as a GIGABYTE GA-MA78G-DS3H though, as the
old PCI IDs and subsystem IDs of match. Thus, use differing ones for
both boards, which is not so easy. The only usable-looking difference
is in the SATA controller subsystem IDs. This should allow us to
properly detect both boards.
Corresponding to flashrom svn r534.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Thanks Myles Watson <mylesgw@gmail.com> for the report.
Corresponding to flashrom svn r532.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
- Document new 'satasii' programmer in -L output and manpage.
- Drop PCI_IO_BASE_ADDRESS, pci.h has such #defines already.
- Beautify flashrom output and make it more consistent.
- Same for the 'make' output (reordered some $CC parameters).
Build-tested on i386, shouldn't break any builds, I think.
- Some variable renaming and other cosmetic fixes.
Corresponding to flashrom svn r529.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
It was easy because
1) flashrom has now nice API 2) documentation is public on the web site
Don't forget to add a files. Because I do.
Corresponding to flashrom svn r528.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
It was easy because
1) flashrom has now nice API 2) documentation is public on the web site
Corresponding to flashrom svn r527.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Corresponding to flashrom svn r525.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
[PATCH] tested SST39VF010
Self-ack is fine for test reports.
Rudolf Marek wrote:
> > Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
Some MMIO accesses used volatile, others didn't (and risked
non-execution of side effects) and even with volatile, some accesses
looked dubious.
Since the MMIO accessor functions and the onboard flash accessor
functions are functionally identical (but have different signatures),
make the flash accessors wrappers for the MMIO accessors.
For some of the conversions, I used Coccinelle. Semantic patch follows:
@@ typedef uint8_t; expression a; volatile uint8_t *b; @@ - b[a] + *(b
+ a) @@ expression a; volatile uint8_t *b; @@ - *(b) |= (a); + *(b) =
*(b) | (a); @@ expression a; volatile uint8_t *b; @@ - *(b) = (a); +
mmio_writeb(a, b); @@ volatile uint8_t *b; @@ - *(b) + mmio_readb(b) @@
type T; T b; @@ ( mmio_readb | mmio_writeb ) (..., - (T) - (b) + b )
Corresponding to flashrom svn r524.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Uwe tested read, write, erase with this patch on a random board to make
sure nothing breaks.
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
- Supported out of the box (no flash enables required)
- Verifiably not yet working (unknown flash enable)
Also, move some structs to flash.h in preparation for later wiki
output support.
Corresponding to flashrom svn r523.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
They serve pretty much no purpose, compilers can optimize pretty much
all of what we might mark as inline anyway, _and_ inlines are not
enforced in any way by the compiler either. They're totally unneeded.
Kill them.
Corresponding to flashrom svn r522.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Build-tested on 32bit x86.
Corresponding to flashrom svn r521.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
This is tested on hardware.
Also, add initial support for the Atmel AT29C010A chip (which I inserted
in a 3COM 3C90xB card for testing). It can be detected, read works,
erase works, but write will need some additional code (will post in
another patch later).
Corresponding to flashrom svn r520.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Use chipaddr instead of volatile uint8_t * because when we access chips
in external flashers, they are not accessed via pointers at all.
Benefits: This allows us to differentiate between volatile machine
memory accesses and flash chip accesses. It also enforces usage
of chip_{read,write}[bwl] to access flash chips, so nobody will
unintentionally use pointers to access chips anymore. Some unneeded
casts are removed as well. Grepping for chip operations and machine
memory operations doesn't yield any false positives anymore.
Compile tested on 32 bit and 64 bit Linux.
Corresponding to flashrom svn r519.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
2.2.8, as it's default on current FreeBSD 7.2) don't properly fill
the base_addr[0] struct member, so revert back to an explicit
pci_read_long() call, otherwise detection of PCI devices and their base
address will fail with strange error messages.
Thanks Idwer Vollering <vidwer@gmail.com> for reporting and testing.
Corresponding to flashrom svn r518.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
The emulation works by splitting 32 bit accesses into 16 bit accesses
and 16 bit accesses into to 8 bit accesses. That way, external flashers
can mix and match the amount of emulation they need.
Corresponding to flashrom svn r517.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
It seems some boards do not use SPI_HOLD at all. Take that into account
when trying to figure out if SPI is available.
Print the SB600 ROM strap override register status for better debugging.
Corresponding to flashrom svn r516.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Move the reusable PCI specific parts into pcidev.c, they'll be usable
for other NIC code (Realtek, VIA, ...) and also for SATA/IDE controller
cards as external programmers (for every PCI device which can program
EEPROMs basically).
Also add print_supported_pcidevs() to show the supported PCI devices
(currently only NICs, soon more) in the 'flashrom -L' output.
Corresponding to flashrom svn r515.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Until the ICH SPI driver can handle preopcodes as standalone opcodes,
we should handle such special opcode failure gracefully on ICH and
compatible chipsets.
This fixes status register writes on almost all ICH+VIA SPI masters.
The fix is almost identical to r484, but this time it affects the EWSR
(Enable Write Status Register) opcode instead of the WREN (Write Enable)
opcode.
With the differentiated return codes introduced in r500, the workaround
is more precise this time. The old WREN workaround was updated as well.
Corresponding to flashrom svn r514.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: FENG Yu Ning <fengyuning1984@gmail.com>
Acked-by: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
If we find multiple ones, abort with a message to the user, suggesting
to use the
flashrom -p nic3com=bb:dd.f
syntax. If exactly one supported NIC is found, use it. If none is found,
abort with an error.
Print the bb:dd.f numbers for all supported NICs we find, so the user
doesn't have to poke around in lspci output to find the desired bb:dd.f.
Also, drop one pci_read_long() in favor of using the already existing
base_addr[0] struct field.
Drop the BAR in user messages, it's not really useful for us. Instead,
explain the BDF syntax a bit more verbosely.
While I'm at it, update the manpage some more to mention and fully
document the external programmer support we have (or will have soon).
The patch is tested on hardware:
$ flashrom -p nic3com flashrom v0.9.0-r512 Found NIC "3COM 3C905C:
EtherLink 10/100 PCI (TX)" (10b7:9200, BDF 05:04.0) Found NIC "3COM
3C905C: EtherLink 10/100 PCI (TX)" (10b7:9200, BDF 05:03.0) Error:
Multiple supported NICs found. Please use 'flashrom -p nic3com=bb:dd.f'
to explicitly select the card with the given BDF (PCI bus, device,
function).
$ flashrom -p nic3com=05:04.0 flashrom v0.9.0-r512 Found NIC "3COM
3C905C: EtherLink 10/100 PCI (TX)" (10b7:9200, BDF 05:04.0) Calibrating
delay loop... OK. Found chip "Atmel AT49BV512" (64 KB) at physical
address 0xffff0000. No operations were specified.
Corresponding to flashrom svn r513.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Factor out portable iopl()-style code into a global function which all
programmers can use, add missing close() call.
Corresponding to flashrom svn r511.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Add support for users to specify a certain NIC via PCI bus:slot.func
notation, in case there are multiple NICs in one system.
Usage: flashrom -p nic3com=bb:ss.f
Corresponding to flashrom svn r510.
Signed-off-by: Christian Ruppert <spooky85@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Build-tested and 'make PREFIX=/tmp/foo install' tested by me.
Corresponding to flashrom svn r509.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Does not support reading or writing the fake chip yet.
flashrom --programmer dummy
also enables the dummy SPI controller driver.
Testing the dummy SPI driver revealed a RDID debug printing bug in the
SPI core. Fix that as well.
Corresponding to flashrom svn r507.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Even if we don't tell the user about the areas the block locking bits
correspond to, printing a detailed list of which lock bits are set is a
definite improvement.
Corresponding to flashrom svn r505.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Sample output:
[...]
Probing for SST SST25VF032B, 4096 KB: RDID returned bf 25 4a.
probe_spi_rdid_generic: id1 0xbf, id2 0x254a
Chip status register is 1c
Chip status register: Block Protect Write Disable (BPL) is not set
Chip status register: Auto Address Increment Programming (AAI) is not
set
Chip status register: Bit 5 / Block Protect 3 (BP3) is not set
Chip status register: Bit 4 / Block Protect 2 (BP2) is set
Chip status register: Bit 3 / Block Protect 1 (BP1) is set
Chip status register: Bit 2 / Block Protect 0 (BP0) is set
Chip status register: Write Enable Latch (WEL) is not set
Chip status register: Write In Progress (WIP/BUSY) is not set
Found chip "SST SST25VF032B" (4096 KB) at physical address 0xffc00000.
Acked-by: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
Downgrade the chips from 256-byte writes to 1-byte writes. This fixes
writing to them on ICH/VIA SPI masters.
Corresponding to flashrom svn r504.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: FENG Yu Ning <fengyuning1984@gmail.com>
