These helpers are only used by the CLI logic and so we localise
them here to move towards cli_classic being a pure libflashrom
user.
BUG=b:208132085
TEST=`make`
Change-Id: If1112155e2421e0178fd73f847cbb80868387433
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
This allows for moving all the do_*() helper functions
use for the cli from flashrom.c within static local functions
in cli_classic.c
BUG=b:208132085
TEST=`make`
Change-Id: Ia0abec655a682ca449d0e8ba620886a2d616b86d
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Inline emergency_help_message() to cli_classic call site.
This leaves do_erase() a redudant wrapper and moves us a step
closer to cli_classic as a pure libflashrom user by using
flashrom_flash_erase().
BUG=b:208132085
TEST=`flashrom -E`
Change-Id: I8566164e7dbad69cf478b24208014f10fb99e4d0
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
The function is only ever used within flashrom.c.
BUG=none
BRANCH=none
TEST=builds
Change-Id: I81f1cdb9df98c151201390edeb69c74defe7881f
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/56295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Rename it to layout_sanity_checks() as that is what it does and
let it work on the currently active layout instead of the global
layout.
Change-Id: Ifae3480d4bd68c939c291f05734544e93f00306c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/54285
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It initializes an empty layout. Currently the maximum number of entries
has to be specified, which will vanish once we use dynamic allocation
per entry.
We replace the two special cases `single_layout` and `ich_layout` with
dynamically allocated layouts. As a result, we have to take care to
release the `default_layout` in a flashctx once we are done with it.
Change-Id: I2ae7246493ff592e631cce924777925c7825e398
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This change introduces a new option to extract all layout regions to
files with the name of each region (or with the provided filename via
-i region:file). It is implemented by mutating the flash layout to
include all regions and backfilling the entry->file with entry->name
(replacing spaces with underscores)
Signed-off-by: Daniel Campello <campello@chromium.org>
Change-Id: I8c69223fa92cf5b50abe070f1ab9f19d3b42f6ff
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Add an optional sub-parameter to the -i parameter to allow building the
image to be written from multiple files. This will also allow regions to
be read from flash and written to separate image files.
This is a rebase of a patch that was ported from chromiumos. A lot of
things have changed, but the idea is the same.
Original patch by Louis Yung-Chieh Lo <yjlou@chromium.org>:
Summary: Support -i partition:file feature for both read and write.
Commit: 9c7525f
Review URL: http://codereview.chromium.org/6611015
Ported version by Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
and Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>:
Summary: [PATCH 2/6] layout: Add -i <region>[:<file>] support.
Review URL: https://mail.coreboot.org/pipermail/flashrom/2013-October/011729.html
Change-Id: Ic5465659605d8431d931053967b40290195cfd99
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Signed-off-by: Daniel Campello <campello@chromium.org>
Co-Authored-by: Edward O'Callaghan <quasisec@google.com>
Co-Authored-by: Daniel Campello <campello@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/23021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Allows drivers to register a callback function to reset the
chip state once programming has finished. This is used by
the s25f driver added in a later patch, which needs to change
the chip's sector layout to be able to write to the entire flash.
Adapted from cros flashrom at
`9c4c9a56b6a0370b383df9c75d71b3bd469e672d`.
BUG=b:153800073
BRANCH=none
TEST=builds
Change-Id: I2a522dc1fd3952793fbcad70afc6dd43850fbbc5
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/47276
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Align with the properly tab indented comment on the CrOS
Flashrom side to make things consisent.
Change-Id: I09605bfec203d294077f298f8619bbc7d10cc68a
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/48204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Seems to be dead code with no call sites.
BUG=none
BRANCH=none
TEST=builds
Change-Id: Ic9f33415b8a357916891cb2006612cbf5e6aa559
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
The following just lays out the structure for write protect
manipulation of SPI flash chips in Flashrom. We later follow
up with adding support for each manufacturer group.
BUG=b:153800563
BRANCH=none
TEST=builds
Change-Id: Id93b5a1cb2da476fa8a7dde41d7b963024117474
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40325
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit a3519561bd0fb44153bb376322b799000657576f.
Breaks support for most SPI flash chips. It's too big and too
invasive to be reviewed as a single commit.
The changes to `spi_poll_wip():spi25.c` were not noticed in the
original review that were from the similarly named function and
file `s25f_poll_status():s25f.c` in the downstream Chromium fork.
V.2: Rebase and rephrase commit msg to reflect how the issue
slipped in.
Change-Id: Id2a4593bdb654f8a26957d69d52189ce61621d93
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shiyu Sun <sshiyu@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The ChromiumOS flashrom fork has since const'ify flashctx
in a few places. This aligns the function signatures to
match with downstream to ease forward porting patches
out of downstream back into mainline flashrom.
This patch is minimum viable alignment and so feedback is
welcome.
Change-Id: Iff6dbda13cb0d941481c0d204b9c30895630fbd1
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40324
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This may seem too big just to support yet another flash chip, but in
reality it brings support for whole new family of S25FS
Spansion/Cypress flash chips. These chips require handling of some
special status registers for erasing or writing, with very specific
timing checks in place.
For example, WIP status bit will remain being set to 1 if erase or
programming errors occur, and in that case chip 'software reset' has
to be performed otherwise the chip will remain unresponsive to all
further commands. Also, special CR3NV register (Configuration Register
3 Nonvolatile) status bits needs to be read and set by using RDAR
(ReaD Any Register) and WRAR (WRite Any Register) OP commands, and
these states are needed to determine which type of reset feature is
enabled at the time (legacy or S25FS type) in the first place,
determine whether Uniform or Hybrid sector architecture is used
at the time, or set programming buffer address wrap point (256 or 512
bytes). Furthermore, S25FS chip status register has to be restored to
its original state (hence that ugly CHIP_RESTORE_CALLBACK) following
erasing or writing, failing to do so may result in host being unable
to access data on the chip at all.
Finally, although this brings support for the whole family of chips,
I only have one such chip to do the actual testing, S25FS128S (Small
Sectors), which I had fully tested on ch341a and FT4232H programmers,
with confirmed working probe, read, erase and write.
Full summary of changes are here:
flashchips:
add new flashchip sctructure property:
.reset
add chip definitions:
S25FS128S Large Sectors
S25FS128S Small Sectors
flash:
add macro (chip_restore_func_data call-back):
CHIP_RESTORE_CALLBACK
flashrom:
add struct:
chip_restore_func_data
add call-back function:
register_chip_restore
spi:
add OP codes:
CMD_RDAR, CMD_WRAR, CMD_WRAR_LEN, CMD_RSTEN, CMD_RST
add register bit function definitions:
CR3NV_ADDR, CR3NV_20H_NV
add timers:
T_W, T_RPH, T_SE
spi25:
refactor (based on chromiumos implementation) function:
spi_poll_wip
port these functions from chromiumos:
probe_spi_big_spansion
s25fs_software_reset
s25f_legacy_software_reset
s25fs_block_erase_d8
spi25_statusreg:
port these functions from chromiumos:
spi_restore_status
s25fs_read_cr
s25fs_write_cr
s25fs_restore_cr3nv
Most of the ported functions are originally from s25f.c found at
https://chromium.googlesource.com/chromiumos/third_party/flashrom
with exception of spi_restore_status which is defined in
spi25_statusreg.c. The rest of macros and OP codes are defined in
same files as in this commit.
Change-Id: If659290874a4b9db6e71256bdef382d31b288e72
Signed-off-by: Samir Ibradzic <sibradzic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Provide strndup implementation if compiled with MinGW because
it is a POSIX only method
Signed-off-by: Miklós Márton <martonmiklosqdev@gmail.com>
Change-Id: If418080bffff1f5961cacf2a300ea9c666682458
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Mostly by changing to `unsigned` types where applicable, sometimes
`signed` types, and casting as a last resort.
Change-Id: I08895543ffb7a48058bcf91ef6500ca113f2d305
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/30409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
We enforced a 16MiB limit in spi_read_chunked() for multi-die flash
chips that can't be fully read at once. The same limit can be useful
for dediprog programmers. So move it into a more generic place.
Change-Id: Iab1fd5b2ea550b4b3ef3e8402e0b6ca218485a51
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33613
Reviewed-by: Ryan O'Leary
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This removes the use of global variables for included region arguments
and also uses a linked list to store the arguments.
Change-Id: I6534cc58b8dcc6256c2730c809286d8083669a6c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/31247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
4BA mode is entered by setting bit 7 for the extended address register.
Change-Id: I807bf55d65763a9f48a6a3377f14f4e5288a7a4c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Tested-by: Michael Fuckner <michael@fuckner.net>
Reviewed-on: https://review.coreboot.org/25133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
The Spansion 25SFL256S supports 4BA through an extended address register,
a 4BA mode set by bit 7 of that register, or native 4BA instructions.
Enable the former only for now.
Unfortunately the S25SF256S uses another instruction to write the exten-
ded address register. So we add an override for the instruction byte.
Change-Id: I0a95a81dfe86434f049215ebd8477392391b9efc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Tested-by: Michael Fuckner <michael@fuckner.net>
Reviewed-on: https://review.coreboot.org/25132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This imports a series of patches from chromiumos for MTD support.
The patches are squashed to ease review and original Change-Ids have
been removed to avoid confusing Gerrit.
There are a few changes to integrate the code:
- Conflict resolution
- Makefile changes
- Remove file library usage from linux_mtd. We may revisit this and use
it for other Linux interfaces later on.
- Switch to using file stream functions for reads and writes.
This consolidated patch is
Signed-off-by: David Hendricks <dhendricks@fb.com>
The first commit's message is:
Initial MTD support
This adds MTD support to flashrom so that we can read, erase, and
write content on a NOR flash chip via MTD.
BUG=chrome-os-partner:40208
BRANCH=none
TEST=read, write, and erase works on Oak
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/272983
Reviewed-by: Shawn N <shawnn@chromium.org>
This is the 2nd commit message:
linux_mtd: Fix compilation errors
This fixes compilation errors from the initial import patch.
Signed-off-by: David Hendricks <dhendricks@fb.com>
This is the 3rd commit message:
linux_mtd: Suppress message if NOR device not found
This just suppresses a message that might cause confusion for
unsuspecting users.
BUG=none
BRANCH=none
TEST=ran on veyron_mickey, "NOR type device not found" message
no longer appears under normal circumstances.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/302145
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This is the 4th commit message:
linux_mtd: Support for NO_ERASE type devices
Some mtd devices have the MTD_NO_ERASE flag set. This means
these devices don't require an erase to write and might not have
implemented an erase function. We should be conservative and skip
erasing altogether, falling back to performing writes over the whole
flash.
BUG=b:35104688
TESTED=Zaius flash is now written correctly for the 0xff regions.
Signed-off-by: William A. Kennington III <wak@google.com>
Reviewed-on: https://chromium-review.googlesource.com/472128
Commit-Ready: William Kennington <wak@google.com>
Tested-by: William Kennington <wak@google.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
This is the 5th commit message:
linux_mtd: do reads in eraseblock-sized chunks
It's probably not the best idea to try to do an 8MB read in one syscall.
Theoretically, this should work; but MTD just relies on the SPI driver
to deliver the whole read in one transfer, and many SPI drivers haven't
been tested well with large transfer sizes.
I'd consider this a workaround, but it's still good to have IMO.
BUG=chrome-os-partner:53215
TEST=boot kevin; `flashrom --read ...`
TEST=check for performance regression on oak
BRANCH=none
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/344006
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This is the 6th commit message:
linux_mtd: make read/write loop chunks consistent, and documented
Theoretically, there should be no maximum size for the read() and
write() syscalls on an MTD (well, except for the size of the entire
device). But practical concerns (i.e., bugs) have meant we don't quite
do this.
For reads:
Bug https://b/35573113 shows that some SPI-based MTD drivers don't yet
handle very large transactions. So we artificially limit this to
block-sized chunks.
For writes:
It's not clear there is a hard limit. Some drivers will already split
large writes into smaller chunks automatically. Others don't do any
splitting. At any rate, using *small* chunks can actually be a problem
for some devices (b:35104688), as they get worse performance (doing an
internal read/modify/write). This could be fixed in other ways by
advertizing their true "write chunk size" to user space somehow, but
this isn't so easy.
As a simpler fix, we can just increase the loop increment to match the
read loop. Per David, the original implementation (looping over page
chunks) was just being paranoid.
So this patch:
* clarifies comments in linux_mtd_read(), to note that the chunking is
somewhat of a hack that ideally can be fixed (with bug reference)
* simplifies the linux_mtd_write() looping to match the structure in
linux_mtd_read(), including dropping several unnecessary seeks, and
correcting the error messages (they referred to "reads" and had the
wrong parameters)
* change linux_mtd_write() to align its chunks to eraseblocks, not page
sizes
Note that the "->page_size" parameter is still somewhat ill-defined, and
only set by the upper layers for "opaque" flash. And it's not actually
used in this driver now. If we could figure out what we really want to
use it for, then we could try to set it appropriately.
BRANCH=none
BUG=b:35104688
TEST=various flashrom tests on Kevin
TEST=Reading and writing to flash works on our zaius machines over mtd
Change-Id: I3d6bb282863a5cf69909e28a1fc752b35f1b9599
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/505409
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Martin Roth <martinroth@chromium.org>
Reviewed-by: William Kennington <wak@google.com>
Reviewed-on: https://review.coreboot.org/25706
Tested-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
The __MINGW_PRINTF_FORMAT constant has been defined back in 2012
77bc5d6103/
However older toolchains are still around and some user reported the
following compilation failure:
flash.h:336:1: error: '__MINGW_PRINTF_FORMAT' is an unrecognized format function type [-Werror=format=]
__attribute__((format(__MINGW_PRINTF_FORMAT, 2, 3)));
Fix this by defining the constant when it isn't already; the change does
not affect other compilers because it's guarded by "#ifdef __MINGW32__".
Setting __MINGW_PRINTF_FORMAT to gnu_printf is exactly what newer MinGW
versions do when __USE_MINGW_ANSI_STDIO is defined, which it is in
flashrom Makefile.
Change-Id: I48de3e4303b9a389c515a8ce230282d9210576fd
Tested-by: Miklos Marton <martonmiklosqdev@gmail.com>
Signed-off-by: Antonio Ospite <ao2@ao2.it>
Reviewed-on: https://review.coreboot.org/25130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
When developing software that has to be flashed to a flash chip to be
executed, it often takes a long time to read the current flash contents
(for flashrom to know what pages to erase and reprogram) each time
when writing the new image. However, when the flash was just reprogrammed,
its current state is known to be the previous image that was flashed
(assuming it was verified).
Thus, it makes sense to provide that image as a file for the flash contents
instead of wasting valuable time read the whole flash each time.
Change-Id: Idf153b6955f37779ae9bfb228a434ed10c304947
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/23263
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ENE Embedded Debug Interface (EDI) is a SPI-based interface for
accessing the memory of ENE embedded controllers.
The ENE KB9012 EC is an embedded controller found on various laptops
such as the Lenovo G505s. It features a 8051 microcontroller and
has 128 KiB of internal storage for program data.
EDI can be accessed on the KB9012 through pins 59-62 (CS-CLK-MOSI-MISO)
when flash direct access is not in use. Some firmwares disable EDI at runtime
so it might be necessary to ground pin 42 to reset the 8051 microcontroller
before accessing the KB9012 via EDI.
The example of flashing KB9012 at Lenovo G505S laptop could be found here:
http://dangerousprototypes.com/docs/Flashing_KB9012_with_Bus_Pirate
Change-Id: Ib8b2eb2feeef5c337d725d15ebf994a299897854
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/23259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Most flash chips are erased to ones and programmed to zeros. However, some
other chips, such as the ENE KB9012 internal flash, work the opposite way.
Change-Id: Ia7b0de8568e31f9bf263ba0ad6b051e837477b6b
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/23258
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
By default, we want to probe for SPI25 chips only. Other SPI use cases,
like the ENE/EDI protocol, might use commands that can confuse these
common chips.
Now, flashrom will probe for a chip only if one of these conditions is
true:
1) no chip has been specified AND the chip uses the SPI25 commands
2) this chip has been specified by -c | --chip <chipname>
The CLI can later be extended to probe for a specific class of chips.
Change-Id: I89a53ccaef2791a2ac32904d7ab813da7478a6f0
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/23262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Kocialkowski <contact@paulk.fr>
Advertise all 4BA features that are currently supported by flashrom,
plus add a new feature flag for the 4BA fast-read instruction. Also,
list all supported 3BA and 4BA erase-block functions.
As this adds a lot of new code paths that could be taken for these
chips, mark them all as untested again.
Change-Id: I0598496ee7058e3b170684d366f58e4014e0e871
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22423
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Instead of arbitrarily deciding whether to enter 4BA mode in the flash
chip's declaration, advertise that entering 4BA mode is supported and
only enter it if the SPI master supports 4-byte addresses. If not, exit
4BA mode (the chip might be in 4BA mode after reset). If we can't assure
the state of 4BA mode, we bail out to simplify the code (we'd have to
ensure that we don't run any instructions that can usually be switched
to 4BA mode otherwise).
Two new feature flags are introduced:
* FEATURE_4BA_ENTER:
Can enter/exit 4BA mode with instructions 0xb7/0xe9 w/o WREN.
* FEATURE_4BA_ENTER_WREN
Can enter/exit 4BA mode with instructions 0xb7/0xe9 after WREN.
FEATURE_4BA_SUPPORT is dropped, it's completely implicit now.
Also, draw the with/without WREN distinction into the enter/exit
functions to reduce code redundancy.
Change-Id: I877fe817f801fc54bd0ee2ce4e3ead324cbb3673
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22422
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Get rid of the layering violations around ICH's BBAR. Move all the weird
address handling into (surprise, surprise) `ichspi.c`. Might fix writes
for the `BBAR != 0` case by accident.
Background: Some ICHs have a BBAR (BIOS Base Address Configuration
Register) that, if set, limits the valid address range to [BBAR, 2^24).
Current code lifted addresses for REMS, RES and READ operations by BBAR,
now we do it for all addresses in ichspi. Special care has to be taken
if the BBAR is not aligned by the flash chip's size. In this case, the
lower part of the chip (from BBAR aligned down, up to BBAR) is inacces-
sible (this seems to be the original intend behind BBAR) and has to be
left out in the address offset calculation.
Change-Id: Icbac513c5339e8aff624870252133284ef85ab73
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22396
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Prefer the native 4BA instruction when they are supported. In this
case, override our logic to decide to use a 4BA address.
Change-Id: I2f6817ca198bf923671a7aa67e956e5477d71848
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22385
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allow 4-byte addresses for instructions usually used with 3-byte
addresses. Decide in which way the 4th byte will be communicated
based on the state of the chip (i.e. have we enabled 4BA mode)
and a new feature bit for an extended address register. If we
are not in 4BA mode and no extended address register is available
or the write to it fails, bail out.
We cache the state of 4BA mode and the extended address register
in the flashctx.
Change-Id: I644600beaab9a571b97b67f7516abe571d3460c1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22384
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
spi_simple_write_cmd() executes WREN plus a single byte write and polls
WIP afterwards. It's used to replace current spi_erase_chip_*() imple-
mentations.
Change-Id: Ib244356fa471e15863b52e6037899d19113cb4a9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
TARGET_OS as well as EXEC_SUFFIX were only set when called via the
main makefile and even then __USE_MINGW_ANSI_STDIO was not set
for MinGW.
While at it, also replace the hardcoded gnu_printf printf format
attribute with __MINGW_PRINTF_FORMAT which is set according to
__USE_MINGW_ANSI_STDIO respectively.
Change-Id: Id146f5ba06a0e510397c6f32a2bd7c819a405a25
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/21838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This allows us to support flash chips in any of the following
configurations, regardless of whether the chip powers up in 3-byte or
4-byte address mode.
- standard commands with extended address register (*_4ba_ereg) or
direct commands (*_4ba_direct) in 3-byte address mode (.set_4ba =
spi_exit_4ba_*)
- standard commands (*_4ba) or direct commands (*_4ba_direct) in
4-byte address mode (.set_4ba = spi_enter_4ba_*)
- direct commands (*_4ba_direct) in either address mode (.set_4ba =
NULL)
Change-Id: I0b25309d731426940fc50956b744b681ab599e87
Signed-off-by: Ed Swierk <eswierk@skyportsystems.com>
Reviewed-on: https://review.coreboot.org/20510
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Large flash chips usually support special instructions to work with
4-bytes address directly from 3-bytes addressing mode and without
do switching to 4-bytes mode. There are 13h (4BA Read), 12h (4BA Program)
and 21h,5Ch,DCh (4BA Erase), correspondingly. However not all these
instructions are supported by all large flash chips. Some chips
support 13h only, some 13h,12h,21h and DCh, but not 5Ch. This depends
on the manufacturer of the chip.
This patch provides code to use direct 4-bytes addressing instructions.
This code should work but it tested partially only. My W25Q256FV has
support for 4BA_Read (13h), but doesn't have support 4BA_Program (12h)
and 4BA_Erase instructions. So, direct 4BA program and erase
should be tested after.
Patched files
-------------
chipdrivers.h
+ added functions declarations for spi4ba.c
flash.h
+ feature definitions added
flashchips.c
+ modified definition of Winbond W25Q256BV/W25Q256FV chips
flashrom.c
+ modified switch to 4-bytes addressing for direct-4BA instructions
spi4ba.h
+ definitions for 4-bytes addressing JEDEC commands
+ functions declarations from spi4ba.c (same as in chipdrivers.h, just to see)
spi4ba.c
+ functions for read/write/erase directly with 4-bytes address (from any mode)
Change-Id: Ib51bcc5de7826b30ad697fcbb9a5152bde2c2ac9
Signed-off-by: Boris Baykov <dev@borisbaykov.com>, Russia, Jan 2014
[clg: ported from
https://www.flashrom.org/pipermail/flashrom/2015-January/013198.html ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-on: https://review.coreboot.org/20508
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On some flash chips data with addresses more than 24-bit field
can address may be accessed by using Extended Address Register.
The register has 1-byte size and stores high byte of 32-bit address.
Then flash can be read from 3-bytes addressing mode with writing
high byte of address to this Register. By using this way we have
access to full memory of a chip. Some chips may support this method
only.
This patch provides code use Extended Address Register.
Patched files
-------------
chipdrivers.h
+ added functions declarations for spi4ba.c
flash.h
+ feature definitions added
flashrom.c
+ modified switch to 4-bytes addressing to support extended address register
spi4ba.h
+ definitions for 4-bytes addressing JEDEC commands
+ functions declarations from spi4ba.c (same as in chipdrivers.h, just to see)
spi4ba.c
+ functions for write Extended Address Register
+ functions for read/write/erase with Extended Address Register
Change-Id: I09a8aa11de2ca14901f142c67c83c4fa0def4e27
Signed-off-by: Boris Baykov <dev@borisbaykov.com>, Russia, Jan 2014
[clg: ported from
https://www.flashrom.org/pipermail/flashrom/2015-January/013200.html ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-on: https://review.coreboot.org/20507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch integrates code of the previous patch into Flashrom's code.
All the integrations is around 3 functions spi_nbyte_read, spi_nbyte_program
and spi_byte_program. After this patch then are not static and can be called
by their pointers saved in flashchips array. Also I added to flashrom.c some
code to switch a chip to 4-bytes addressing mode. And one error message is
corrected in spi.c because it's not suitable for 32-bit addresses.
Patched files
-------------
flash.h
+ added set of 4-bytes address functions to flashchip structure definition
flashrom.c
+ added switch to 4-bytes addressing more for chips which support it
serprog.c
+ added 4-bytes addressing spi_nbyte_read call to serprog_spi_read
spi.c
+ fixed flash chip size check in spi_chip_read
spi25.c
+ added 4-bytes addressing spi_nbyte_read call to spi_read_chunked
+ added 4-bytes addressing spi_nbyte_program call to spi_write_chunked
+ added 4-bytes addressing spi_byte_program call to spi_chip_write_1
Conflicts:
serprog.c
Change-Id: Ib051cfc93bd4aa7580519e0e6206d025f3ca8049
Signed-off-by: Boris Baykov <dev@borisbaykov.com>, Russia, Jan 2014
[clg: ported from
https://www.flashrom.org/pipermail/flashrom/2015-January/013205.html ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-on: https://review.coreboot.org/20505
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix some whitespace, and braces. Remove sector size from comments that I
could not verify.
Change-Id: I4faaa036fea744135fa37f405686fb9fd0882806
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
If flash chip is switched to 4-bytes addressing mode then all
read/erase/program instructions will be switched from 3-bytes mode
to 4-bytes mode. Then well known instructions like 03h (Read),
02h (Program) and 20h,52h,D8h (Erase) will become one byte longer
and accept 4-bytes address instead of 3-bytes.
This patch provides support for well known instructions in 4-bytes
addressing mode. Also here is the code to enter 4-bytes addressing
mode by execute the instruction B7h (Enter 4-bytes mode).
Patched files
-------------
chipdrivers.h
+ added functions declarations for spi4ba.c
flash.h
+ feature definitions added
Makefile
+ added spi4ba.c
Added files
-----------
spi4ba.h
+ definitions for 4-bytes addressing JEDEC commands
+ functions declarations from spi4ba.c (same as in chipdrivers.h, just to see)
spi4ba.c
+ functions for enter 4-bytes addressing mode
+ functions for read/write/erase in 4-bytes addressing mode
Change-Id: Ie72e2a89cd75fb4d09f48e81c4c1d927c317b7a7
Signed-off-by: Boris Baykov <dev@borisbaykov.com>, Russia, Jan 2014
[clg: ported from
https://www.flashrom.org/pipermail/flashrom/2015-January/013199.html ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-on: https://review.coreboot.org/20513
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
o Move flashbuses_to_text() to flashrom.c, it's not a cli function.
o Guard `!defined(HAVE_STRNLEN)`. This guard was introduced in
23e10b87 (Add a bunch of new/tested stuff and various small
changes 24) to support older BSDs. It's probably completely
broken because HAVE_STRNLEN is presumably a GNU autotools
thing. But we can't fix it without retesting these older BSDs.
Change-Id: I561135209b819361d125eeaeef9ff886d6bae987
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18738
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add an option --ifd to read the ROM layout from an Intel Firmware
Descriptor (IFD). Works the same as the -l option, if given, -i
specifies the images to update.
v2: o Rebased on libflashrom, use libflashrom interface.
o Use functions from ich_descriptors.c.
v3: o Move ich_descriptors.o to LIB_OBJS, thus build it independent
of arch and programmers.
o Bail out if we aren't compiled for little endian.
o Update flashrom.8.tmpl.
v4: o Incorporated David's comments.
o Removed single-character `-d` option.
v5: Changed region names to match the output of `ifdtool --layout ...`
Change-Id: Ifafff2bf6d5c5e62283416b3269723f81fdc0fa3
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
