I can confirm a successful reading and writing of MX25L8005 (SPI) on a HP t5550
Thin Client (AMI BIOS 786R9 v1.04).
Change-Id: I190253b0c1920747b710ed7155e78191cce139eb
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/23030
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Avoid attempting to read the SPI bases from the location 0x00000000, all
zeroes mean that the chipset's MMIO area is not enabled.
Change-Id: I5d3a1ba695153e854e0979ae634f8ed97e6b6293
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/23029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This patch has been tested on a board similar to AMD Bettong.
00:14.0 SMBus [0c05]: Advanced Micro Devices, Inc. [AMD] FCH SMBus
Controller [1022:790b] (rev 4a)
00:14.3 ISA bridge [0601]: Advanced Micro Devices, Inc. [AMD] FCH LPC
Bridge [1022:790e] (rev 11)
root@qt5022-fglrx:~# ./flashrom -p internal -w kk.rom
flashrom v0.9.9-unknown on Linux 4.10.0-qtec-standard (x86_64)
flashrom is free software, get the source code at
https://flashrom.org
Calibrating delay loop... OK.
coreboot table found at 0x9ffd6000.
Found chipset "AMD FP4".
Enabling flash write... OK.
Found Micron/Numonyx/ST flash chip "N25Q128..1E" (16384 kB, SPI)
mapped at physical address 0x00000000ff000000.
Reading old flash chip contents... done.
Erasing and writing flash chip... Erase/write done.
Verifying flash... VERIFIED.
Change-Id: I66a240ebc8382cc7e5156686045aee1a9d03fe6d
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-on: https://review.coreboot.org/21429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This adds PCI IDs for C620-series PCHs and adds
CHIPSET_C620_SERIES_LEWISBURG as a new entry in the ich_chipset enum.
Lewisburg is very similar to Sunrise Point for Flashrom's purposes,
however one important difference is the way the "number of masters" is
interpreted from the flash descriptor (0-based vs. 1-based). There are
also new flash regions defined.
Change-Id: I96c89bc28bdfcd953229c17679f2c28f8b874d0b
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/20922
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The pci_dev structure is never meant to be used as is, but always as a
pointer. By using the struct itself in undo_pci_write_data, we are risking
data corruption, or buffer overflows if the structure size changes.
This is especially apparent on my system where flashrom segfaults
because I compile it with pciutils 3.3.0 and I run it on a system
with pciutils 3.5.2. The struture size is different and causes a
struct with the wrong size to be sent to the library, with invalid
internal field values.
This has been discovered and discussed in Change ID 18925 [1]
[1] https://review.coreboot.org/#/c/18925/
Change-Id: Icde2e587992ba964d4ff92c33aa659850ba06298
Signed-off-by: Youness Alaoui <kakaroto@kakaroto.homelinux.net>
Reviewed-on: https://review.coreboot.org/20784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
All publicly known Skylake / Kabylake / Sunrise Point PCH variants
share the same register interface [1..6]. Although all SPI configu-
ration is now done through the SPI PCI device 1f.5, we can't probe
for it directly since its PCI vendor and device IDs are usually hid-
den.
To work around the hidden IDs, we use another PCI accessor that doesn't
rely on the OS seeing the PCI device.
This handles SPI flashes only. While booting from LPC is still sup-
ported, it seems nobody uses it any more.
Some additional PCI IDs were gathered from driveridentifier.com.
TEST=Compiled with B150 set to NT (instead of BAD) and checked for
sane register readings.
[1] 6th Generation Intel® Core(TM) Processor Families I/O Platform
Datasheet - Volume 1 of 2
Revision 002EN
Document Number 332995
[2] 6th Generation Intel® Processor I/O Datasheet for U/Y Platforms
Volume 2 of 2
Revision 001EN
Document Number 332996
[3] 7th Generation Intel® Processor Families I/O Platform
Datasheet - Volume 1 of 2
Revision 002
Document Number 334658
[4] 7th Generation Intel® Processor Families I/O for U/Y Platforms
Datasheet - Volume 2 of 2
Revision 002
Document Number 334659
[5] Intel® 100 Series and Intel® C230 Series Chipset Family Platform
Controller Hub (PCH)
Datasheet - Volume 1 of 2
Revision 004EN
Document Number 332690
[6] Intel® 100 Series Chipset Family Platform Controller Hub (PCH)
Datasheet - Volume 2 of 2
Revision 001EN
Document Number 332691
Change-Id: I000819aff25fbe9764f33df85f040093b82cd948
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18925
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
It's never used and has no clear contract (e.g. will the pointer stay
valid beyond the call?).
Change-Id: I0d4e7cc731364e86eff214b9022b842a577f9ef4
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The subtle difference was ignored when adding these chipsets. The
integrated Wildcat Point LP PCH is documented in [1].
I'm not sure how to account for "Broadwell H" which seems not publicly
documented. Maybe it's an unreleased HM9*, in which case the non-LP
path should be correct.
[1] Mobile 5th Generation Intel® Core(TM) Processor Family I/O,
Intel® Core(TM) M Processor Family I/O, Mobile Intel® Pentium® Processor
Family I/O, and Mobile Intel® Celeron® Processor Family I/O Datasheet
Revision 004
Document Number: 330837
Change-Id: I6b7ca3c0bde111b04ed7c745ed76d28d3d05f01c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18883
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GCS was decoded partly inside, partly outside this function. The
decoding of `top_swap` was off, since passing a `uint8_t` as `bool`
doesn't magically check bit0 only.
While we are at it, rename this void function to enable_flash_ich_
report_gcs() as it's not doing anything. Beside debug output it
doesn't have any side effects.
Change-Id: I40addec98cb6840763adad30f9d0e27dadce6d1e
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18882
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Tested mainboards:
OK:
- ASRock G31M-GS
Reported by Александр Трубицын
- ASRock G41M-VS3
Reported by Александр Трубицын
- ASRock N68C-S UCC
Reported by Alexey Belyaev
- ASRock AMCP7AION-HT (ION 330HT(-BD))
Reported by Stefan Tauner
- ASUS P5K SE
Reported by Александр Трубицын
- ASUS P5KPL-VM
Reported by Marin Vlah
- ASUS RAMPAGE III GENE
Reported by stevessss on IRC
- GIGABYTE GA-945GM-S2
Reported by Александр Трубицын
- GIGABYTE GA-945GCM-S2 (rev. 3.0)
Reported by Александр Трубицын
- GIGABYTE GA-965P-S3
Reported by Александр Трубицын
- GIGABYTE GA-EG43M-S2H
Reported by Александр Трубицын
- GIGABYTE GA-EP31-DS3L (rev. 1.0)
Reported by Александр Трубицын
- GIGABYTE GA-G33M-S2
Reported by Александр Трубицын
- GIGABYTE GA-G33M-S2L
Reported by Александр Трубицын
- GIGABYTE GA-H55M-S2
Reported by Александр Трубицын
- GIGABYTE GA-J1900N-D3V
Reported by Marcos Truchado and Guillermo von Hünefeld
- GIGABYTE GA-K8NS
Reported by nicolae788
- GIGABYTE GA-M56S-S3
Reported by Estevo Paz Freire
- GIGABYTE GA-P31-DS3L
Reported by Александр Трубицын
- GIGABYTE GA-P31-S3G
Reported by Александр Трубицын
- MSI MS-7336
Reported by Benjamin Bellec
- MSI X79A-GD45 (8D) (MS-7760)"
Reported by mortehu on IRC
- Supermicro A1SAi-2550F
Reported by Bernard Grymonpon
- Supermicro X7DWT
Reported by Steven Stremciuc
Laptop:
- ASUS U38N
Reported by Ultra on IRC
- Dell Latitude D630
Reported by Márton Miklós
- Fujitsu Amilo Xi 3650
Reported by Elmar Stellnberger
- Lenovo T400 (whitelisting only)
Chipsets:
- Mark 8086:1f38 (Intel Avoton/Rangeley) as tested
Reported by Jeremy Porter and Bernard Grymonpon
- Add Intel Sunrise Point IDs but no support yet.
Flash chips:
- Atmel AT45DB321D to PREW (+PREW)
Reported by The Raven
- Eon EN25QH32 to PREW (+PREW)
Reported by Josua Mayer
- Eon EN25QH64 to PREW (+EW)
Reported by David s. Alessio
- GigaDevice GD25LQ64(B) to PREW (+PREW)
Reported by Greg Tippit
- Intel 28F001BN/BX-T to PREW (+EW)
Reported by Lu Xie
- Micron M25P10-A to PREW (+W)
Reported by the Raven
- Micron M25PE40
Reported by David Wood
- Micron N25Q128..3E to PREW (+PREW)
Reported by Miklós Márton
- Macronix MX25L3273E to PREW (+PREW)
Reported by Roklobsta on IRC
- Macronix MX23L6454 to PR (+PR)
Reported by Steven Honeyman
- Macronix MX25U6435E/F to PREW (+PREW)
Reported by Marcos Truchado and Guillermo von Hünefeld
- PMC Pm25LQ032C to PREW (+EW)
Reported by Dirk Knop
- Spansion S25FL016A to PREW (+EW)
Reported by Márton Miklós
- Spansion S25FL128S......0 to PREW (+PREW)
Reported by Jim Houston
- Spansion S25FL204K to PR (+PR)
Reported by Thomas Debrunner
- SST SST49LF016C to PREW (+EW)
Reported by Steven Stremciuc
- SST SST39VF040 to PREW (+PREW)
Reported by Xavier Bourgeois
- SST SST49LF040B to PREW (+EW)
Reported by Rikard Åhlund
- ST M25P10-A to PREW (+W)
Reported by Martijn Schiedon
- Winbond W39V040FA to PREW (+EW)
Reported by Евгений Черкашин
- Winbond W39V080FA to PREW (+EW)
Reported by protagonist0 on IRC
- Winbond W25Q80.W to PREW (+PREW)
Reported by Miklós Márton
- Winbond W25X64 to PREW (+REW)
Reported by Johannes Krampf and Manuel Dejonghe
- Fix ID of AMIC A25LQ64
Reported by Roman Titov
- Fix page size of Spansion S25FL129P......1
Copy and paste error from the 128S uniform 256kB variant, probably.
- Add Micron/Numonyx phase-change memory IDs
Miscellaneous:
- Detect Android target OS.
No changes are required to build flashrom (excluding programmers
with NEED_PCI) on Android.
- Update rayerspi (spipgm) URL
- Fix max_data_write handling of at45db.
- Minor refinement of the README
- Mark board enable for the GA-K8NS variants as tested.
Tested by "nicolae788" on a board with socket 754.
- Mark "Multi-system" chassis as non-laptop case.
- Remove W836xx log requests.
We got enough (and no one is looking at them for the time being anyway).
- serprog: improve invalid reply error message, contributed by Urja Rannikko.
- Remove default include paths for MinGW.
- Disable implicit rules in the Makefile because we don't need them and they
just make the build (imperceptibly) slower.
- Enable our own strnlen() implementation not only on DJGPP but also if
HAVE_STRNLEN is not defined. This is needed to get older BSDs
(e.g. NetBSD 6.0, FreeBSD < 8.0) to work.
- Tiny other stuff.
Corresponding to flashrom svn r1917.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Seems to work on IBM SurePOS 700 and
IBM (now Toshiba) AnyPlace Kiosk Model 4838-310.
Tested-by: Jason Vannest <Jason_Vannest@abercrombie.com>
Tested-by: Rowlinson Mark <Mark.Rowlinson@uk.fujitsu.com>
Corresponding to flashrom svn r1900.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested mainboards:
OK:
- AOpen UK79G-1394 (used in EZ18 barebones)
Reported by Lawrence Gough
- ASUS M4N78 SE
Reported by Dima Veselov
- ASUS P5LD2-VM
Mark board enable as tested (reported by Dima Veselov)
- GIGABYTE GA-970A-UD3P (rev. 2.0)
Reported by trucmar on IRC
- GIGABYTE GA-990FXA-UD3 (rev. 4.0)
Reported by ROKO__ on IRC
- GIGABYTE GA-H77-DS3H (rev. 1.1)
Reported by Evgeniy Edigarev
- GIGABYTE GA-P55-USB3 (rev. 2.0)
Reported by Måns Thörnqvist
- MSI MS-7817 (H81M-E33)
Reported by Igor Kolker
Chipsets:
- Marked Intel Bay Trail (0x0f1c) as tested OK
Reported by Antonio Ospite
- Refine Intel IDs
* Add IDs for Braswell
* Add IDs for 9 Series PCHs (e.g. H97, Z97)
* Rename Wellsburg devices slightly
Flash chips:
- Atmel AT25DF041A to PREW (+PREW)
Reported by Tai-hwa Liang
- Atmel AT26DF161 to PREW (+EW)
Reported by Steve Shenton
- Atmel AT45DB011D to PREW (+PREW)
Reported by The Raven
- Atmel AT45DB642D to PREW (+PREW)
Reported by Mahesh Mokal
- Eon EN25F32 to PREW (+PREW)
Reported by Arman Khodabande
- Eon EN25F40 to PREW (+REW)
Reported by Jerrad Pierce
- Eon EN25QH16 to PREW (+EW)
Reported by Ben Johnson
- GigaDevice GD25Q20(B) to PREW (+PREW)
Reported by Gilles Aurejac
- Macronix MX25U6435E/F to PR (+PR)
Reported by Matt Taggart
- PMC Pm25LV512(A) to PREW (+PREW)
Reported by The Raven
- SST SST39VF020 to PREW (+PREW)
Reported by Urja Rannikko
- Winbond W25Q40.V to PREW (+EW)
Reported by Torben Nielsen
- Add E variants of MX25Lx006 (MX25L2006E, MX25L4006E, MX25L8006E).
- Add MX25L6465E variant.
- There was never a MX25L12805 AFAICT.
- Split MX25L12805 from models with the same ID but an additional 32 kB
eraser: MX25L12835F/MX25L12845E/MX25L12865E.
- Add a bunch of ST parallel NOR flash chip IDs.
Miscellaneous:
- Whitelist ThinkPad X200.
- Constify master parameter of register_master().
- Remove FEATURE_BYTEWRITES because it was never used at all.
- Refine hwseq messages and make them less prominent.
- Fix the yet unused PRIxCHIPADDR format string thingy.
- Fix copy&paste error in spi_prettyprint_status_register_bp().
Spotted by Pablo Cases.
- Add an additional SMBus controller revision to identify another Yangtze
model. Thanks to Dan Christensen for reporting this issue.
- dediprog: add missing include for stdlib.h.
This fixes (at least) building on FreeBSD and DragonflyBSD with gcc.
- Remove references to struct pci_filter from programmer.h.
It is only needed in internal.c where it has a complete type. Having
it in programmer.h provokes a warning by some old versions of gcc.
- Tiny other stuff.
Corresponding to flashrom svn r1879.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
The Wildcat Point PCH can be paired with Broadwell or Haswell.
This patch was essentially backported from ChromiumOS commit 9bd2af8.
Corresponding to flashrom svn r1845.
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
The core of this patch to support Bay Trail originally came from the
Chromiumos flashrom repo and was modified by Sage to support the
Rangeley/Avoton parts as well.
Because that was not complicated enough already Stefan Tauner refactored
and refined everything. Bay Trail seems to be the first Atom SoC able to
support hwseq. No SPI Programming Guide could be obtained so it is
handled similarly to Lynx Point which seems to be its nearest relative.
Corresponding to flashrom svn r1844.
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Tested-by: Marc Jones <marcj303@gmail.com>
Tested-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Tested-by: Thomas Reardon <thomas_reardon@hotmail.com>
Tested-by: Wen Wang <wen.wang@adiengineering.com>
Acked-by: Marc Jones <marcj303@gmail.com>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Tested mainboards:
OK:
- ASUS F2A85-M
Reported by various corebooters
- ASUS M2N-MX SE Plus
Reported by Antonio
- ASUS P5LD2
Reported by François Revol
- Lenovo ThinkPad T530
Reported and partially authored by Edward O'Callaghan
- MSI MS-7502 (Medion MD8833)
Reported by naq on IRC
- Shuttle AB61
Reported by olofolleola4
- ZOTAC IONITX-F-E
Reported by Bernardo Kuri
Flash chips:
- Atmel AT45DB021D to PREW (+PREW)
Reported by The Raven
- Atmel AT25F4096 to PREW (+PREW)
Reported by 공준혁
- GigaDevice GD25Q16(B) to PREW (+PREW)
Reported by luxflow@live.com using a GD25Q16BSIG
- Catalyst CAT28F512
Mark erase and write as known bad (not implemented)
Miscellaneous:
- Various spelling corrections by Daniele Forsi.
- Added and refined a bunch of chips originally investigated by Carl-Daniel.
- Marked the ARM-USB-OCD-H programmer as tested
(reported by Ruud Schramp).
- Tiny other stuff.
Corresponding to flashrom svn r1839.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Corresponding to flashrom svn r1829.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
This should get rid of extra and/or missing line breaks in verbose(+)
output on Intel chipsets.
Corresponding to flashrom svn r1826.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
We got enough (and no one is looking at them for the time being anyway).
Also, return an error code in the case no bus type could be detected.
Corresponding to flashrom svn r1820.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Mark all ME-enabled Intel chipsets as DEP, alter print.c accordingly
(print_wiki.c was already prepared). And realign the chipset enable
table when we are at it already.
Corresponding to flashrom svn r1815.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested mainboards:
OK:
- abit BX6 2.0
Reported by Stefan Tauner
- Acer EM61SM/EM61PM (used in Acer Aspire T180)
Reported by Benjamin Bellec
- ADLINK Express-HR
Reported by Obermair Thomas
- ASUS M3N-H/HDMI
Reported by Franc Serres
- Attro G5G100-P
Reported by Christoph Grenz
- ASRock 960GM-GS3 FX
Reported by Fuley Istvan
- Elitegroup P6BAP-A+ (V2.2)
Reported by Arnaldo Pirrone
- Elitegroup GeForce7050M-M (V2.0)
Reported by Leif Middelschulte
- Fujitsu D3041-A1 (used in ESPRIMO P2560)
Reported by Daggi Duck
- GIGABYTE GA-8S648
Reported by TeslaBIOS
- GIGABYTE GA-970A-D3P (rev. 1.0)
Reported by Jean-Francois Pirus
- GIGABYTE GA-B85M-D3H
Reported by Mladen Milinković
- GIGABYTE GA-X79-UD3
Reported by Jeff O'Neil
- GIGABYTE GA-X79-UP4 (rev. 1.0)
Reported by George Spelvin
- GIGABYTE GA-Z68MA-D2H-B3 (rev. 1.3)
Reported by Vangelis Skarmoutsos
- GIGABYTE GA-Z87-HD3
Reported by virii5
- Lenovo Tilapia CRB
Reported by jenkins56 on IRC
- MSI GT60-2OD (notebook, only with layout patches)
Reported by Vasiliy Vylegzhanin
- MSI MS-6704 (845PE Max2 PCB 1.0) (Pure Version w/o raid)
Reported by professorll
- MSI MS-7399 1.1 (used in Acer Aspire M5640/M3640)
Reported by Koen Rousseau
- MSI MS-7125 (K8N Neo4(-F/FI/FX))
We had a board enable for that one for years, but it was not (and still is not)
completely clear which boards are covered.
- MSI MS-7522 (MSI X58 Pro-E)
Reported by Gianluigi Tiesi
- PCWARE APM80-D3
Reported by César Augusto Jakoby
- Pegatron IPP7A-CP
Reported by Илья Шипко
- Supermicro H8QME-2
Reported by Greg Tippitt
- Supermicro X7SPA-H
Reported by Kyle Bentley
- Supermicro X7SPE-HF-D525
Reported by Micah Anderson
- Supermicro X8DTE
Reported by Mark Nipper
- Supermicro X8SIL-F
Reported by Peter Samuelson
- ZOTAC IONITX-A (-E) version
Reported by Maciej Wroniecki
NOT OK:
- Supermicro X10SLM-F
Reported by Micah Anderson
Flash chips:
- Atmel AT29C020 to PREW (+PREW)
It was marked like that in the past, but I could not find the reason why the
test bits were reset. Urja Rannikko tested it again and it still works.
- Eon EN25F10 to PREW (+PREW)
Reported by Stolmár Tamás
- Eon EN25QH64 to PR (+PR)
Reported by Vladimir 'φ-coder' Serbinenko
- GigaDevice GD25Q32(B) to PREW (+PREW)
Reported by mrnuke
- Macronix MX25L512(E)/MX25V512(C) to PREW (+PREW)
Reported by Jamie Nichol
- Macronix MX25L2005(C) to PREW (+PREW)
Reported by Давыдов Дмитрий
- Micron/Numonyx/ST N25Q064..1E to PREW (+PREW)
Reported by Paolo Zambotti
- Pmc Pm25LD010(C) to PREW (+PREW)
Reported by Vasile Ceteras
- Micron/Numonyx/ST M25P16 to PREW (+EW)
Reported by raven
- Micron/Numonyx/ST M25PX64 to PREW (+W)
Reported by Zaolin
- SST SST25VF020B to PREW (+PREW)
Reported by Michaël Zweers
- SST SST49LF040 to PREW (+W)
Reported by Oskar Enoksson
- Add support for MX25L3273E (evil twin of MX25L3205 et al.)
Also, add MX25L1673 and MX25L6473E to the names of their twins and
add a note about MX25L8073E.
- Winbond W25X32 to PREW (+REW)
Reported by The Raven
- Winbond W29C010 etc. to PREW (+W)
Reported by san
Chipsets tested OK:
- Intel NM70 (8086:1e5f)
Reported by mrnuke
- Intel C204 (8086:1c54)
Reported by Vasiliy Vylegzhanin
- Intel QM67 (8086:1c4f)
Reported by Obermair Thomas
- Intel HM77 (8086:1e57)
Reported by Vasiliy Vylegzhanin
- Intel B85 (8086:8c50)
Reported by Mladen Milinković
- Intel HM87 (8086:8c4b)
Reported by Vasiliy Vylegzhanin
- Intel Z87 (8086:8c44)
Reported by virii5
- NVIDIA MCP51 (10de:0261)
Reported by Marcin Kościelnicki
- SiS 648 (1039:0648)
Reported by TeslaBIOS
Miscellaneous:
- Mark ARM-USB-TINY-H as tested in ft2232_spi (reported by _nanodev_).
- getrevision.sh: Ignore failing date calls.
- getrevision.sh: Fix -u and -l for older git versions which require = for the
git log grep parameter.
- Corrected K8T Neo2-F entries due to a report from Stelios Tsampas.
- Add "-p internal" to output that requests users to send flashrom -V logs.
- Add Macbook2,1, Thinkpad X230, EasyNote LM85 to laptop whitelist.
- Tiny other stuff.
Corresponding to flashrom svn r1783.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
- Combine enable_flash_ich_4e() and enable_flash_ich_dc() to
enable_flash_ich_fwh().
- Remove unjustified (chipset) name parameters from various
enable_flash_ich* functions.
- Make Poulsbo and Tunnel Creek use generic enables by refining existing
functions to work with them, including everything in ichspi.c.
- Refactor enable_flash_ich_fwh_decode() to be called unconditionally for
all chipsets.
- Add support for Intel Atom Centerton (S12x0).
- Recombine ICH2/3/4/5 to CHIPSET_ICH2345 because we treat them equally
anyway.
- Move spibar handling out of ich_init_spi() into enable_flash_ich_spi()
- Various small cleanups.
Corresponding to flashrom svn r1761.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Register locations are different from ICH6, but otherwise appear
to have identical bit specifications and defaults.
Corresponding to flashrom svn r1748.
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Follow the style used from ICH7 onwards to pass ich_generation
parameter to lower-level functions on older ICH chipsets too.
Corresponding to flashrom svn r1747.
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
ICH2 (and C-ICH)/3/4/5 also have FWH_SEL1/2 registers but at
different addresses. In preparation for implementing fwh_idsel
parsing for older ICH chipsets extract the parameter handling
and add variables for the offsets.
While FWH_DEC_EN1 is a 16bit register for ICH6, it is two separate
8bit registers on ICH5 and earlier. Implement all accesses with two
byte instructions instead, to prepare for extended support.
Corresponding to flashrom svn r1746.
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
The only call path where exit was reached was from physmap functions.
Callers of physmap() et al. which were not prepared to handle
ERROR_PTR return values have been adjusted.
physmap_try_ro() has been renamed to physmap_ro() and physmap_common()
slightly refactored due to the now removed *FAIL parameters.
Corresponding to flashrom svn r1745.
Signed-off-by: Niklas Söderlund <niso@kth.se>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
These support an additional bit which we did not turn on yet.
Without this patch they decode up to 512 kB, with this up to 1 MB.
Disentangle the enables of unrelated but mostly compatible chipsets
too, add some more debug output and set the max_rom_decode limits.
Also, make warnings really only warnings.
Corresponding to flashrom svn r1739.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Similarly to the previous PCI self-clean up patch this one allows to get rid
of a huge number of programmer shutdown functions and makes introducing
bugs harder. It adds a new function rphysmap() that takes care of unmapping
at shutdown. Callers are changed where it makes sense.
Corresponding to flashrom svn r1714.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
The PCI ID of the LPC bridge doesn't change between Hudson-2/3/4 and
Yangtze (Kabini/Temash) but the SPI interface does. Bail out in case we
detect Yangtze and add infrastructure to distinguish other families too for
further refactorings.
Also, add ASRock IMB-A180 to the laptop whitelist and refine the IMC
warning a bit.
Tested on ASRock IMB-A180 with and w/o USE_YANGTZE_HEURISTICS, and
by Chris Goodrich from Sage on
- SB600
- SB700
- SB800
- Hudson 3 (A70M)
- Kabini
Corresponding to flashrom svn r1706.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
New IDs taken from Intel's patches for the Linux kernel.
Also, refine original Lynx Point naming etc.
Corresponding to flashrom svn r1656.
Based on the chromiumos patch
Change-Id: I303a05baa80e4449e70d20adf78ebc7128b88d8e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Also, unify all outputs of "Warning:" and "Error:" to use normal
capitalization instead of mixing it with all capitals.
Corresponding to flashrom svn r1643.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Idwer Vollering <vidwer@gmail.com>
Tested Mainboards:
OK:
- Foxconn P55MX
http://www.flashrom.org/pipermail/flashrom/2012-October/010002.html
Tested flash chips:
- Eon EN25F64 to PR (+PR)
http://paste.flashrom.org/view.php?id=1426
- Macronix MX25L1005 to PREW (+PREW)
http://www.flashrom.org/pipermail/flashrom/2012-October/010004.html
- Set SST39VF512 to PREW (+W)
http://www.flashrom.org/pipermail/flashrom/2012-September/009958.html
Tested chipsets:
- Z77 (only reading was really tested)
Miscellaneous:
- Fix ft2232_spi's parameter parsing.
- Fix nicrealtek's init (always segfaulted since r1586 oops).
- Add another T60 variant to the laptop whitelist.
- Improve message shown when image file size does not match flash chip
- Refine messages regarding the flash descriptor override strap according
to the findings by Vladislav Bykov on his P55MX.
- Fix the ID of EN25F64.
- Demote and clarify debug message in serprog_delay().
- Minor other cleanups.
Corresponding to flashrom svn r1613.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
We made a first step into this direction in r1405, but failed to
notice that there was already an extended patch by Jonathan which
was refined to become this one.
Allows the removal of board_shuttle_fn25 (which was also intended to be
used on the ASUS A8N-SLI Deluxe, but this was never tested).
Corresponding to flashrom svn r1593.
A previous iteration was tested on CK804 and
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
which was then
Acked-by: Stefan Reinauer <stepan@coreboot.org>
Rebasing, refining and making errors non-fatal is
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
This patch also changes semantics: previously failing to set this was interpreted as
a fatal error by enable_flash_ck804 and enable_flash_mcp55 although the output
indicated otherwise. Also, in enable_flash_nvidia_nforce2 there was no check
if settings the bit succeeds.
Now all methods check for success and return ERROR_NONFATAL on failure.
Corresponding to flashrom svn r1592.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
This patch just fixes a limited number of bits not conforming to c99 by using
- __asm__ instead of just asm
- {0} instead of {} for struct initialization
- h_addr_list[0] instead of h_addr to access the host address in
struct hostent
- #include <strings.h> where needed (for ffs and strcasecmp)
Based on a previous patch by Carl-Daniel.
Corresponding to flashrom svn r1585.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This is based on chromiumos commit a5f4e82c59d6bcaf06b94623e5516d1db8cb843a.
http://git.chromium.org/gitweb/?p=chromiumos/third_party/flashrom.git;a=commit;h=a5f4e82c59d6bcaf06b94623e5516d1db8cb843a
See also http://www.flashrom.org/pipermail/flashrom/2011-November/008191.html
Besides disabling the SMM protection this also fixes something that bothered
me for a long time: the content of BIOS_CNTL was shown before we try to modify
it. This is usually not what interests us and contradicts other outputs.
With this patch we try to set the write enable and disable the SMM protection
first and show the state of BIOS_CNTL afterwards.
We now return an error only if the write enable is not set (which should be
equivalent to the previous behavior on sane hardware, but it seems to be
'more correct' and makes the code clearer to do this explicitly).
Corresponding to flashrom svn r1582.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Helge Wagner's patch that added VIA VX900 chipset support made me look
closer at the datasheets which led to some concise documentation about
newer VIA chipsets: http://flashrom.org/VIA
Based on that this patch adds full support for VX800/VX820, VX855/VX875
and VX900, including SPI and LPC. VT8237S was not changed (SPI support
only) because there is no public datasheet and it is not clear how to
distinguish between LPC and SPI strapping and investigations in (NDAed)
documents have not brought up anything conclusively.
enable_flash_vt823x could probably be enhanced too due to various
ignored LPC options of the chipset.
Corresponding to flashrom svn r1578.
Signed-off-by: Helge Wagner <Helge.Wagner@ge.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Tested-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
I looked at the datasheet to be sure that the strap names (SPI, PCI,
LPC) are the same as on the series 5 and 6 chipsets.
Corresponding to flashrom svn r1553.
Signed-off-by: Helge Wagner <Helge.Wagner@ge.com>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Move hwaccess.h #include from flash.h to individual drivers.
libflashrom users need flash.h, but they do not care about hwaccess.h
and should not see its definitions because they may conflict with
other hardware access functions and #defines used by the libflashrom
user.
Corresponding to flashrom svn r1549.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
