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216 Commits

Author SHA1 Message Date
Victor Lim
8685230caa flashchips: adding GD25LB512MF/GD25LR512MF 
GD25LB512MF: 1.8V 512Mbit shipped with Quad enabled.
https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20231213/DS-01012-GD25LB512MF-Rev1.0.pdf

GD25LR512MF: all GD25LB512MF features + RPMC feature
The datasheet is identical with GD25LB512MF for the NOR flash side.

Tested both models on ch347 with erase, read, write, and protection.

Change-Id: I6a0061a43af5966c93c95645b51a640c00f3d829
Signed-off-by: Victor Lim <vlim@gigadevice.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83899
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2024-08-17 08:06:19 +00:00
Bora Guvendik
e4cb19a489 flashchips: add support for MX77U51250F chip 
Add initial support for Macronix MX77U51250F.

BUG=none
BRANCH=none
TEST= Tested read, write and probe on google/fatcat with internal
programmer.

Change-Id: I2c2e94f01dc63f60cf636bc6afe1f033e2a6f83c
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/82626
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: DZ <danielzhang@mxic.com.cn>
 2024-08-17 08:05:54 +00:00
Victor
126de26b44 flashchips: add GD25LB512ME 
Added GD25LB512ME to Flashchips.C
added Sames as GD25LB512ME to GIGADEVICE_GD25LR512ME to flashchips.h

GD25LB512ME is 1.8V 512Mbit, Quad enabled when shipped.
https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230627/DS-00580-GD25LB512ME-Rev1.5.pdf

Tested on ch347 with erase, program, read, and protection.

Change-Id: I04103814f901478098c1a989f4239792b64073ec
Signed-off-by: Victor Lim <vlim@gigadevice.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
 2024-08-15 12:51:44 +00:00
Victor
03090fec0a flashchips: add GD25LF256F 
added GD25LF256F on flashchips.c
added GIGADEVICE_GD25LF256F=0x6319 on flashchip.h

GD25LF256F is a higher performance 1.8V 256Mbit SPI flash

I have tested on CH347 with erase, program, read, protection.

Change-Id: I21a71606476e823faa38a7920aa2b10e25d68d26
Signed-off-by: Victor <vlim@gigadevice.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
 2024-08-09 12:59:12 +00:00
Michael Heimpold
d3f9c258db flashchips: add support for chip model Winbond W25Q32JV_M 
This is a 4 MiB model with QE=0 factory setting.

Tested with ch341a programmer: probe, read, write, erase

Link to datasheet:
https://www.winbond.com/resource-files/W25Q32JV%20RevI%2005042021%20Plus.pdf

Change-Id: I374c466848eabf5647dc88e016ac32b99ec37a06
Signed-off-by: Michael Heimpold <mhei@heimpold.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
 2024-07-30 12:28:59 +00:00
Ssunk
ff656e08e5 flashchips: Add Support for XMC XM25QU512C/XM25QU512D 
Add initial support for the SPI flash chip XM25QU512C/XM25QU512D
Datasheet link: https://www.xmcwh.com/uploads/808/XM25QU512C_V1.6.pdf

Tested with ch341a programmer: probe, read, write, erase

Change-Id: I251c66b5d3b4fc94242c2c9d6b7c0f03c1bd7d0b
Signed-off-by: Kan Sun <ssunkkan@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
 2024-07-26 08:29:13 +00:00
Ssunk
1865ac28a3 flashchips: Add Support for XMC XM25QH512C/XM25QH512D 
Add initial support for the SPI flash chip XM25QH512C/XM25QH512D
Datasheet link: https://www.xmcwh.com/uploads/803/XM25QH512C_V1.6.pdf

Tested with ch341a programmer: probe, read, write, erase

Change-Id: Ica8ed5eaba2435a9416274b94f633ea40dfeea2f
Signed-off-by: Kan Sun <ssunkkan@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83242
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2024-07-26 08:28:47 +00:00
Ssunk
a7606f014a flashchips: Add Support for XMC XM25QU256D 
Add initial support for the SPI flash chip XM25QU256D (same as XM25QU256C)
Datasheet link:
https://www.xmcwh.com/uploads/224/XM25QU256C%20_%20Ver%202.0.pdf

Tested with ch341a programmer: probe, read, write, erase

Change-Id: I504699160f804cfbacd189409596e105752d94eb
Signed-off-by: Kan Sun <ssunkkan@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
 2024-07-26 08:24:57 +00:00
Ssunk
806e76477f flashchips: Add Support for XMC XM25QH256D 
Add initial support for the SPI flash chip XM25QH256D (same as XM25QH256C)
Datasheet link:
https://www.xmcwh.com/uploads/802/XM25QH256C%20_%20Ver%202.0.pdf

Tested with ch341a programmer: probe, read, write, erase

Change-Id: I77481e63eb98ed12935288dc0d6286cb1baf8edb
Signed-off-by: Kan Sun <ssunkkan@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83240
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2024-07-26 08:23:28 +00:00
Ssunk
4465fe6356 flashchips: Add Support for XMC XM25QU128D 
Add initial support for the SPI flash chip XM25QU128D (same as XM25QU128C)
Datasheet link: https://www.xmcwh.com/uploads/227/XM25QU128C_Ver2.1.pdf

Tested with ch341a programmer: probe, read, write, erase

Change-Id: If5fe2b3c1973599aecb80adcb5f0fe2dec0da0e5
Signed-off-by: Kan Sun <ssunkkan@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
 2024-07-26 08:20:18 +00:00
Ssunk
c864c10625 flashchips: Add Support for XMC XM25QH128D 
Add initial support for the SPI flash chip XM25QH128D (same as XM25QH128C)
Datasheet link: https://www.xmcwh.com/uploads/801/XM25QH128C_Ver2.1.pdf

Tested with ch341a programmer: probe, read, write, erase

Change-Id: Ia4577fba545f9f8eea15eef7060bd5955a8457ca
Signed-off-by: Kan Sun <ssunkkan@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83238
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2024-07-26 08:19:20 +00:00
Ssunk
3e7d4743ae flashchips: Add Support for XMC XM25QH64D 
Add initial support for the SPI flash chip XM25QH64D (same as XM25QH64C)
Datasheet link: https://www.xmcwh.com/uploads/800/XM25QH64C_Ver1.8.pdf

Change-Id: Ia3357cb2c30cbe34dcf0e06fd037064304b4c0c4
Signed-off-by: Kan Sun <ssunkkan@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
 2024-07-26 08:17:33 +00:00
Ssunk
029951e08d flashchips: Add Support for XMC XM25QU32C 
Add initial support for the SPI flash chip XM25QU32C
Datasheet link: https://www.xmcwh.com/uploads/233/XM25QU32C_Ver2.1.pdf

Tested with ch341a programmer: probe, read, write, erase

Change-Id: Ida0ab895309ef83dcc6b3f03c032a16f9b1f923a
Signed-off-by: Kan Sun <ssunkkan@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
 2024-07-26 08:14:16 +00:00
Ssunk
2f7edbf6fe flashchips: Add Support for XMC XM25QH32C/XM25QH32D 
Add initial support for the SPI flash chip XM25QH32C/XM25QH32D
Datasheet link: https://www.xmcwh.com/uploads/799/XM25QH32C_Ver2.1.pdf

Tested with ch341a programmer: probe, read, write, erase

Change-Id: Ib201ac28384b8db6539e2a82e6f90462d1393208
Signed-off-by: Kan Sun <ssunkkan@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
 2024-07-26 08:10:27 +00:00
Ssunk
7432b540c1 flashchips: Add Support for XMC XM25QU16C 
Add initial support for the SPI flash chip XM25QU16C
Datasheet link: https://www.xmcwh.com/uploads/804/XM25QU16C_%20Ver1.8.pdf

Tested with ch341a programmer: probe, read, write, erase

Change-Id: I0989b5dd239dd32f93e1a338a70e5d7279127d8d
Signed-off-by: Kan Sun <ssunkkan@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
 2024-07-26 08:06:53 +00:00
DanielZhang
04d0259ef1 flashchips: Add support for MXIC MX25U25645G 
The MX25U25645G has been tested by ch341a programmer : read, write,
erase and wp.

We have tested --wp-enable, --wp-disable, --wp-list and --wp-range
commands for write-protect feature.

MX25U25645G datasheet is available at the following URL:
https://www.mxic.com.tw/Lists/Datasheet/Attachments/8738/MX25U25645G,%201.8V,%20256Mb,%20v1.4.pdf

Change-Id: I8641f36e1909274629690fc243be46281a21360d
Signed-off-by: DanielZhang <danielzhang@mxic.com.cn>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/82777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
 2024-07-26 08:04:02 +00:00
Ssunk
4b1611afbe flashchips: Add Support for XMC XM25QH16C/XM25QH16D 
Add initial support for the SPI flash chip XM25QH16C/XM25QH16D
Datasheet link: https://www.xmcwh.com/uploads/798/XM25QH16C_Ver1.8.pdf

Tested with ch341a programmer: probe, read, write, erase

Change-Id: I215084ed33ca9261f6c7b91ef868ca8db85e61ad
Signed-off-by: Kan Sun <ssunkkan@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83182
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2024-06-27 21:18:18 +00:00
Ssunk
a89d2f906b flashchips: Add Support for XMC XM25QU80B 
Add initial support for the SPI flash chip XM25QU80B
Datasheet link: https://www.xmcwh.com/uploads/520/XM25QU80B_Ver1.4.pdf

Tested with ch341a programmer: probe, read, write, erase

Change-Id: I8350f4ba94b4819e6496b9c5fddc8617bc0528b5
Signed-off-by: Kan Sun <ssunkkan@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83180
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2024-06-27 00:50:30 +00:00
Subrata Banik
57cd50cd6a ichspi: Add support for Panther Lake 
This patch adds Panther Lake support into flashrom as per Intel
Panther Lake SPI programming doc, number: 815466.

BUG=b:347669091
TEST=Flashrom is able to detect PTL SPI DID and show chipset name as
below:

> flashrom --flash-name
....
Found chipset "Intel Panther Lake-U/H 12Xe".
....
> flashrom -p internal --ifd -i fd -i bios -r /tmp/bios.rom
....
Reading ich_descriptor... done.
Assuming chipset 'Panther Lake'.
Using regions: "bios", "fd".
Reading flash... done.
SUCCESS

Change-Id: I99cd8eb7cbb11381f8e8455b06cf90b9db77d8f0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83144
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
 2024-06-27 00:44:06 +00:00
Michael Heimpold
332c5d0671 flashchips: add support for chip model Winbond W25Q16JV_M 
This is a 2 MiB model with QE=0 factory setting.

Tested with ch341a programmer: probe, read, write, erase

Link to datasheet:
https://www.winbond.com/resource-files/w25q16jv%20spi%20revh%2004082019%20plus.pdf

Change-Id: Ida1ceb5fe31411bef647e5133c5bd0bdb02d7704
Signed-off-by: Michael Heimpold <mhei@heimpold.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/82715
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2024-06-12 02:18:18 +00:00
DanielZhang
acd6a326cb flashchips: Add support for MXIC MX25R4035F 
The MX25R4035F has been tested by ch341a programmer : read, write,
erase and wp.

We have tested --wp-enable, --wp-disable, --wp-list and --wp-range
commands for write-protect feature.

MX25R4035F datasheet is available at the following URL:
https://www.macronix.com/Lists/Datasheet/Attachments/8671/MX25R4035F,%20Wide%20Range,%204Mb,%20v1.4.pdf

Change-Id: I91dbc4735bf232e0b1dce72c7f06be967d35ebfb
Signed-off-by: DanielZhang <danielzhang@mxic.com.cn>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/81838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
 2024-06-02 08:22:31 +00:00
Georg Gottleuber
47de5d71bc flashchips.c: Add support for XM25RU256C 
Tested read, write and erase with ch341a_spi programmer (and 1.8V
adapter).

Test log:
https://paste.flashrom.org/view.php?id=3729

Change-Id: I431474a662304d09438e274706d3fc9cfbbe0bd6
Signed-off-by: Georg Gottleuber <ggo@tuxedocomputers.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/82101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
 2024-06-01 13:18:40 +00:00
Robert Marko
7fcae77732 flashchips: Add XTX XT25F128B 
XTX XT25F128B is 128M-bit version of XT25F64B.
Tested probe, read, erase and write with FT232H.

Datasheet: https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2304140030_XTX-XT25F128BSSIGT_C558844.pdf

Change-Id: I37084bd66bc7a8f93d6533ab0d67aa2528786299
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/82676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
 2024-06-01 08:42:00 +00:00
Peter Marheine
d7e4240263 Add clarification to struct flash_region on chipoff_t 
Although chipoff_t is fairly clearly documented on its own, it seems
fairly frequent that developers will treat the end address of a flash
region as an exclusive upper bound rather than the inclusive one it
should be; for example CB:82496 fixes an incorrect use that affected
multiple sites, and CB:73571 stemmed from a similar cause. Add a
clarifying comment to call attention to this, to help programmers avoid
making similar mistakes in the future.

Change-Id: I80b61a87ca31bd5a116224aadb4e211ee6841e1f
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/82677
Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2024-05-31 00:27:07 +00:00
Peter Marheine
510ef74653 tests/erase: record the opcode for each erase 
This allows tests to verify that the correct opcode is used when
erasing, which is required to unit-test the fix to issue #525 where in
some situations an incorrect erase opcode will be used.

BUG=https://ticket.coreboot.org/issues/525

Change-Id: I3983fe42c2e7f06668a1bd20d2db7fafa93b8043
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/82251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
 2024-05-31 00:25:27 +00:00
Ravi Sarawadi
2f8e64372a flashchips: Add support for GigaDevice GD25LR256E, GD251R512ME 
BUG=none
BRANCH=none
TEST= Flash image using Flashrom Tool

flashrom -p raiden_debug_spi -w <test_binary>
flashrom -p dediprog -w <test_binary>

Also tested by two people on the mailing list:
https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/TCT534OIVOFZ2HHIJ4LSADQPS27ENCG2/

Change-Id: I2fe6bc1219cd1ee19b93caabab69de938cfc44b0
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
 2024-05-24 08:21:48 +00:00
Victor Lim
a83d996f76 flashchips: Add support for chip model GD25LF128E 
Adding GD25LF128E to flashchip.c

GD25LF128E: 1.8V 128Mbit, QE default fixed at 1.
Datasheet link
https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230627/DS-00632-GD25LF128E-Rev1.3.pdf

Change-Id: I71fdc7ea1aea69d14db6af3bac2da3e7bee8abbe
Signed-off-by: Victor Lim <vlim@gigadevice.com>
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/82332
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2024-05-23 11:28:28 +00:00
boyesm
86752777d5 flashchips: Add support for Boya B25Q64AS 
The B25Q64AS has been tested by ch341a programmer: read, write, erase

Datasheet: https://archive.org/details/1912111437-boyamicro-by-25-q-64-assig-c-383793

Change-Id: I05ecf2b118902db974544d86e023a348912371dd
Signed-off-by: Malcolm Boyes <boyesmalcolm@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/82259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
 2024-05-23 11:28:00 +00:00
roccochen@chromium.com
85b977151b ichspi.c: Add support for region 9 and beyond in Meteor Lake 
Since Meteor Lake, configuring region access for FREG9 and higher is
necessary. This configuration is determined using BIOS_BM registers:

BIOS_BM_RAP (Offset 0x118): BIOS Master Read Access Permissions.
Each bit [15:0] corresponds to a region [15:0].
A set bit grants BIOS master read access.

BIOS_BM_WAP (Offset 0x11c): BIOS Master Write Access Permissions.
Each bit [15:0] corresponds to a region [15:0].
A set bit grants BIOS master write/erase access.

Move CHIPSET_METEOR_LAKE to the bottom of the ich_chipset list to ensure
that all the newer chipsets in the future will use BIOS_BM check by
default.

BUG=b:319773700, b:304439294
BUG=b:319336080
TEST=On MTL, use flashrom -VV to see correct FREG9 access
TEST=On ADL, use flashrom -VV to see not break anything
TEST=On APL, use flashrom -VV to see not break anything

Change-Id: I1e06e7b3d470423a6014e623826d9234fdebfbf9
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/81357
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2024-05-19 09:07:50 +00:00
DanielZhang
adeaaf6b5d flashchips: Add support for MXIC MX25R2035F 
The MX25R2035F has been tested by ch341a programmer : read, write,
erase and wp.

We have tested --wp-enable, --wp-disable, --wp-list and --wp-range
commands for write-protect feature.

MX25R2035F datasheet is available at the following URL:
https://www.macronix.com/Lists/Datasheet/Attachments/8696/MX25R2035F,%20Wide%20Range,%202Mb,%20v1.6.pdf

Change-Id: I00e76ef942976e3e102cf71fe695c6287b392b64
Signed-off-by: DanielZhang <danielzhang@mxic.com.cn>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/81839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
 2024-05-12 11:22:32 +00:00
DanielZhang
e558ef1fb9 flashchips: Add support for MXIC MX25L1633E 
The MX25L1633E has been tested by ch341a programmer : read, write,
erase and wp.

We have tested --wp-enable, --wp-disable, --wp-list and --wp-range
commands for write-protect feature.

MX25L1633E datasheet is available at the following URL:
https://www.macronix.com/Lists/Datasheet/Attachments/8617/MX25L1633E,%203V,%2016Mb,%20v1.8.pdf

Change-Id: I63ee0182ad6e62b7408136285aa0e927d53f7bc8
Signed-off-by: DanielZhang <danielzhang@mxic.com.cn>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/81836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
 2024-05-03 02:36:02 +00:00
DanielZhang
c2bb2eff4c flashchips: Add support for MXIC MX25L3239E 
The MX25L3239E has been tested by ch341a programmer : read, write,
erase and wp.

We have tested --wp-enable, --wp-disable, --wp-list and --wp-range
commands for write-protect feature.

MX25L3239E datasheet is available at the following URL:
https://www.mxic.com.tw/Lists/Datasheet/Attachments/8613/MX25L3239E,%203V,%2032Mb,%20v1.3.pdf

Change-Id: Ic7a848028fe937deb1bf83ef2a9dddf1330334b6
Signed-off-by: DanielZhang <danielzhang@mxic.com.cn>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/81563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
 2024-04-29 09:17:44 +00:00
Peter Marheine
183208b5cb udelay: only use OS time for delays, except on DOS 
As proposed on the mailing list ("RFC: remove the calibrated delay
loop" [1]), this removes the calibrated delay loop and uses OS-based
timing functions for all delays because the calibrated delay loop can
delay for shorter times than intended.

When sleeping this now uses nanosleep() unconditionally, since usleep
was only used on DOS (where DJGPP lacks nanosleep).  When busy-looping,
it uses clock_gettime() with CLOCK_MONOTONIC or CLOCK_REALTIME depending
on availability, and gettimeofday() otherwise.

The calibrated delay loop is retained for DOS only, because timer
resolution on DJGPP is only about 50 milliseconds. Since typical delays
in flashrom are around 10 microseconds, using OS timing there would
regress performance by around 500x. The old implementation is reused
with some branches removed based on the knowledge that timer resolution
will not be better than about 50 milliseconds.

Tested by reading and writing flash on several Intel and AMD systems:

 * Lenovo P920 (Intel C620, read/verify only)
 * "nissa" chromebook (Intel Alder Lake-N)
 * "zork" chromebook (AMD Zen+)

[1]: https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/HFH6UHPAKA4JDL4YKPSQPO72KXSSRGME/

Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: I7ac5450d194a475143698d65d64d8bcd2fd25e3f
Reviewed-on: https://review.coreboot.org/c/flashrom/+/81545
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
 2024-04-25 23:23:01 +00:00
DanielZhang
6f47cc1737 flashchips: Add support for MXIC MX25R8035F 
The MX25R8035F has been tested by ch341a programmer : read, write,
erase and wp.

We have tested --wp-enable, --wp-disable, --wp-list and --wp-range
commands for write-protect feature.

MX25R8035F datasheet is available at the following URL:
https://www.macronix.com/Lists/Datasheet/Attachments/8749/MX25R8035F,%20Wide%20Range,%208Mb,%20v1.6.pdf

Change-Id: Iec244ffc29278c1f8c3ae47d17af2c4fe5fbe498
Signed-off-by: DanielZhang <danielzhang@mxic.com.cn>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/81837
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2024-04-22 05:12:40 +00:00
DanielZhang
1bcedfa598 flashchips: Add support for MXIC MX25L12850F 
The MX25L12850F has been tested by ch341a programmer : read, write,
erase and wp.

We have tested --wp-enable, --wp-disable, --wp-list and --wp-range
commands for write-protect feature.

MX25L12850F datasheet is available at the following URL:
https://www.macronix.com/Lists/Datasheet/Attachments/8632/MX25L12850F,%203V,%20128Mb,%20v1.0.pdf

Change-Id: I71ac70d273904f94d015401f9d8df587084efad0
Signed-off-by: DanielZhang <danielzhang@mxic.com.cn>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/81350
Reviewed-by: Alexander Goncharov <chat@joursoir.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
 2024-03-30 07:57:37 +00:00
Anton Samsonov
b65f347377 flashchips: Add Zetta Device ZD25LQ128 
Datasheet: http://www.zettadevice.com/uploads/files/163410630201e3483211247ac1.pdf

Tested probe, read, erase, write, verify on ZD25LQ128AWIG chips
using Linux SPI and DediProg SF100 programmers.

Renamed ZETTADEVICE_ macros to ZETTA_ to accomodate longer suffixes.

Change-Id: I5cb20158e81ab109f16958285b8787858efb4831
Signed-off-by: Anton Samsonov <devel@zxlab.ru>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/81392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
 2024-03-26 05:34:52 +00:00
Davide Gerhard
f08acc669b flashchips: Add Macronix MX25R1635F 
16Mbit (2MiB) [x1/x2/x4] Wide Voltage Range (VCC 1.65V-3.6V). It is
similar to the already-supported MX25R3235F, but the total size is
halved.

Tested probe, read, erase, write and verify with buspirate.

Datasheet: https://www.mxic.com.tw/Lists/Datasheet/Attachments/8702/MX25R1635F,%20Wide%20Range,%2016Mb,%20v1.6.pdf

Change-Id: Idce301ed90d6742b56e928068d201e5c3a2e5aee
Signed-off-by: Davide Gerhard <rainbow@irh.it>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/69678
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2024-02-07 06:16:49 +00:00
Tyler Wang
6f3339fda6 flashchips: Add GD25LQ255E 
datasheet: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20221129/DS-00562-GD25LQ255E-Rev1.1.pdf

BUG=b:311336475
TEST=(1) flashrom -p internal -r /tmp/bios.bin, get "SUCCESS" result
     (2) flashrom -p internal -w /tmp/bios.bin, get "SUCCESS" result
     (3) flashrom -i RW_MRC_CACHE -E, get "SUCCESS" result

Change-Id: I0d780255ed6772f4aa406584acf071a7ddd6da47
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/79088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
 2024-01-05 03:54:45 +00:00
Anton Samsonov
8efe4fb708 Remove dependency on C23 __has_include() 
Use build system to check header presence:
* getopt.h (from include/cli_classic.h)
* pciutils/pci.h (from include/platform/pci.h)

Tested with <getopt.h> and <pci/pci.h> using GNU Make 4.1, 4.2.1, 4.4.1
and Meson 0.56.0, 1.2.1 against GCC 13.2.1 and GCC 5.5-, 7.3-compatible
(EDG 4.14-, 5.1-based) on openSuSE Tumbleweed and a custom LFS distro.

Change-Id: Ic544963ffd29626ae0a21bdddb1c78850cc43ec6
Signed-off-by: Anton Samsonov <devel@zxlab.ru>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/77089
Reviewed-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-11-28 23:26:01 +00:00
Hsuan Ting Chen
abd9a1e9e8 flashchips: Split GD25Q127C/GD25Q128C and add GD25Q128E 
Q127C and Q128C are not the same. Q127C doesn't support QPI but Q128C
does. So we need to split the existing GD25Q127C/GD25Q128C into two
separated entries. We also introduce the new flashchip Q128E and merge
it into Q127C.

Datasheets:
Q128E: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00480-GD25Q128E-Rev1.2.pdf
Q127C: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00220-GD25Q127C-Rev2.3.pdf
Q128C: https://www.endrich.com/sixcms/media.php/2/GD25Q128C-Rev2.pdf

Q128E and Q127C/Q128C have compatible main functions, their differences
are:
* Q128E uses 55 nm process, while Q127C/Q128C use 65nm
* Q128E/Q127C does not support QPI
* Q128E/Q127C have OTP: 3072B, while Q128C are 1536B
* Q128E's fast read clock frequency is 133MHz, while Q127C/Q128C are
  104MHZ

So we decided to merge Q128E into Q127C.

We also tested that Q128E could pass flashrom_tester while probing it as
127C/128C, so the main functionalities are compatible.

Change the chip name from GD25Q127C/GD25Q128C to two entries
GD25Q127C/GD25Q128E and GD25Q128C to make it more accurate.

Chip revision history:
- The 'GD25Q127C/GD25Q128C' definition was added in
  `commit e0c7abf219b81ad049d09a4671ebc9196153d308` as 'GD25Q128C' and
  later renamed to 'GD25Q127C/GD25Q128C'

BUG=b:304863141, b:293545382
BRANCH=none
TEST=flashrom_tester with flashrom binary could pass with Q128E,
     which contains probe, read, write, erase, and write protect

Signed-off-by: Hsuan Ting Chen <roccochen@google.com>
Change-Id: I3300671b1cf74b3ea0469b9c5a833489ab4914f5
Reviewed-on: https://review.coreboot.org/c/flashrom/+/78348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
 2023-11-19 23:23:46 +00:00
Alexander Goncharov
8a7f8ade46 spi25_statusreg: rename amic_a25l032 print to a generic name 
Other chips (at least Winbond) will benefit from this change.

Also, drop the FIXME comment, as it can be misleading. The
"pretty print" functions should only display values from the
Status Register, so using an inappropriate function might only
confuse user.

Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Change-Id: I7169a2312698343e1065cdca91a3985e00cb3804
Reviewed-on: https://review.coreboot.org/c/flashrom/+/78874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
 2023-11-18 20:52:05 +00:00
WereCatf
52b794ff26 flashchips: Add Puya P25Q21H/11H/06H 
Datasheet:
https://semic-boutique.com/wp-content/uploads/2016/05/P25Q21H-SSH-IT.pdf

Tested P25Q21H read, write and probe with CH341a.

Signed-off-by: Nita Vesa <werecatf@outlook.com>
Change-Id: Idd43145c72607837cb7afa1b007e68eb8e63ebd9
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58134
Reviewed-by: Alexander Goncharov <chat@joursoir.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-11-05 23:56:33 +00:00
Patrick Rudolph
1dd7c88f41 ichspi: Add support for C740 PCH 
Clean commit 51e1d0e4b7
'Add support for Intel Emmitsburg PCH' which broke
CHIPSET_5_SERIES_IBEX_PEAK detection and which assumes C740 is the same
as C620, while its more a close relative to Intel's H570 PCH.

Based on Intel SPI Programming Guide #619386.

Test: Run on Intel ArcherCity CRB with Intel's C741 PCH
      using the 'internal' programmer.
Test: Run on BMC and accessed the SPI flash chip over
      'linux_mtd' programmer.
Change-Id: I80eebc0fcc14de9df823aceaee77870ad136f94a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/78186
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-10-25 10:03:31 +00:00
Sungbo Eo
9ccbf1cf43 flashchips: Add support for XMC XM25QH80B 
XM25QH80B has the same ID as M45PE80, but has more features.
Tested with CH341A.

Change-Id: Ib51225426d8d1a381d45af3574e5ba2bf02837aa
Signed-off-by: Sungbo Eo <mans0n@gorani.run>
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63516
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-22 05:32:40 +00:00
xianzheng
ebda447ad9 flashchips: Add support for MXIC MX25U25643G 
It is similar to the MX25U25635F and shares its RDID.

Tested by ch341a programmer : read, write and erase.

Datasheet is available at the following URL:
https://www.mxic.com.tw/en-us/products/NOR-Flash/Serial-NOR-Flash/Pages/spec.aspx?p=MX25U25643G&m=Serial%20NOR%20Flash&n=PM2832

Change-Id: Ie04a5e2325aab94bffb276675be3fa4a88c6e134
Signed-off-by: xianzheng <xianzheng@mxic.com.cn>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/76853
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-17 09:06:17 +00:00
Neil Armstrong
aa468cf0bd flashchips: add definition of the XT25F02E SPI NOR flash 
This adds definition of the XT25F02E 2MBit SPI NOR Flash
from XTX Technology Limited.

Tested (Probe, Erase, Write, Read) with a VL805 USB3.0 bridge.

Datasheet:
https://datasheet.lcsc.com/lcsc/2006091008_XTX-XT25F02EDTIGT_C596313.pdf

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Change-Id: I295633c448c05520e4a6aa09c08bd7c9f2346d54
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/50263
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-09-16 08:41:46 +00:00
Vasily Galkin
86907148c6 flashchips.c: Add support for IS25WQ040 
Based on https://github.com/flashrom/flashrom/pull/204
squashed with fixes of IS25WQ040 size: it is 4Mbits, not 4MBytes, see
https://www.issi.com/WW/pdf/25WQ020-040.pdf

Tested read, write and erase with ft2232_spi-based "Tigard" programmer.

Change-Id: I072c6b94d7931637d1c2721c3316205f2d57320e
Signed-off-by: Roman Stingler <roman.stingler@gmail.com>
Signed-off-by: Vasily Galkin <galkin-vv@ya.ru>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58179
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-30 08:53:40 +00:00
Joseph C. Lehner
2bfc85b2a6 flashchips: add Macronix MX25L3255E 
Tested using the linux_spi programmer on a Raspberry Pi.

Datasheet:
https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L3255E.pdf

Signed-off-by: Joseph C. Lehner <joseph.c.lehner@gmail.com>
Change-Id: I65968771e22e6b823d2d6192c33f5b0cba25d5b9
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/57410
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-23 09:43:05 +00:00
Angel Pons
8a3db802ea flashchips: Add ISSI IS25LQ016 
Datasheet: http://www.issi.com/WW/pdf/25LQ016.pdf
Tested all four PREW functions with a FT2232H.

Change-Id: I02f19767b8a60fb2d37adab34894b6edb6ac4494
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
 2023-08-15 06:11:21 +00:00
Anastasia Klimchuk
9917fa0623 flash: Update the comment for flashchip eraseblocks 
Change-Id: Ica7790667ac4c1baf961cb7a330e08178e2c0c28
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/75744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aarya <aarya.chaumal@gmail.com>
 2023-07-27 02:18:18 +00:00