Tested reading, writing and erasing the internal flash chip using an HP
280 G2 SFF mainboard with an Intel H110 PCH. However, since ME-enabled
chipsets are marked as DEP instead of OK, this one shall also be.
Change-Id: I5deac6e43a43ee9748aaa7dadae50065613488b1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/48384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested probe/read/erase/write operations succeed with cros
flashrom on rikku chromebox. Marking as DEP to follow
convention for ME-enabled chipsets.
BUG=b:170906609
BRANCH=none
TEST=Applied patch to cros flashrom and verified that
`flashrom -VV` no longer prints a chipset warning on rikku
Change-Id: I0b4d1dd2b271537faea15856442fe183d9de3318
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/47218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested reading, writing and erasing the internal flash chip using an HP
Elite 8200 mainboard with an Intel Q67 PCH. However, since ME-enabled
chipsets are marked as DEP instead of OK, this one shall also be.
Change-Id: I2bd431c5c72824654b6b5b840f9af55dfe9d3554
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/47797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Modified to be pch7 over pch6 as per-coreboot and review
comments.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic69dc024e9af0c43d6b3a8213a5dc5d2f898c447
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/47090
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Port from the ChromiumOS fork of flashrom.
Change-Id: I8075fe5f80ac0da5280d2f0de6829ed3a2496476
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Support for the Intel C620 Series Chipset SPI Controller (rev 04) is added
to enable SPI flash access on the following platform:
- Intel Xeon D-2187NT
Support for this controller was shortly tested on the platform above.
The flash is recognized, some regions of the flash are locked.
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Tested-by: Jakov Petrina <jakov.petrina@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Change-Id: If39d9bb1acd4029f802a44a2940dd23f66ba09b1
Reviewed-on: https://review.coreboot.org/c/flashrom/+/44162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Commit 92d6a86 ("Refactor Intel Chipset Enables") eliminated a check
to disable SPI when ICH7 has booted from LPC, as the hardware does not
support it. Therefore, when flashrom probes the SPI bus, it times out
waiting for the hardware to react, for each and every SPI flash chip.
This results in very long delays and countless instances of the error:
Error: SCIP never cleared!
To prevent this, bring back part of the lost check. Probing for LPC and
FWH when booted from SPI does not seem to cause any problems on desktop
mainboards with ICH7, so don't disable LPC nor FWH if that is the case.
Tested on ECS 945G-M4 (ICH7, boots from LPC), works without errors.
Change-Id: I5e59e66a2dd16b07f2dca410997fce38ab9c8fd1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested reading, writing and erasing the internal flash chip using an
Acer Aspire ES1-572 laptop with an Intel i3-6006U. However, since all
ME-enabled chipsets are marked as DEP instead of OK, this one shall
follow suit as well.
Change-Id: Ib8ee9b5e811df74d2f48bd409806c72fe862bc24
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Intel Ice Lake systems use an 495 Series Chipset
that behaves compatible to pch300 chips but chip names
are undocumented at this point.
This change was tested in read/write/erase on the Razer
Blade Stealth (late 2019) with intel 1065G7 CPU and
"Ice Lake U Premium PCH".
Change-Id: I6227d32f4476420cf1aeec37ebd4b7648e0b3d15
Signed-off-by: Johanna Schander <git@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/37987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christoph Pomaska <github@slrie.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Intel Kaby Lake U (with the 9d4e device id) support is available but
marked not tested.
Tested reading, writing and erasing both internal flash chips on the
Facebook Monolith system with the Intel i3 7100U SoC. However, since all
ME-enabled chipsets are marked as DEP instead of OK, this one shall follow
suit as well.
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Change-Id: Ie35cc896e29baffa63fe9e37c14770001b54e7ec
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38481
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested reading, writing and erasing the internal flash chip using a
Samsung NP530U3C laptop with an Intel HM76 PCH. However, since all
ME-enabled chipsets are marked as DEP instead of OK, this one shall
follow suit as well.
Change-Id: I1097c5fcf782e7ecf52f05c571ad188456307d00
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/37803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested reading, writing and erasing the internal flash chip using an HP
Pro 6300 SFF mainboard with an Intel Q75 PCH. However, since ME-enabled
chipsets are marked as DEP instead of OK, this one shall also be.
Change-Id: I273af0eb33e74b31bc4fdc95362527bba080c5a0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/35826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The usual ME-lock limitations apply, so this is DEP instead of OK.
Tested on Kontron/bSL6 (SKL) and Siemens/Field PG M6 (CFL) and also
regression tested on Apollo Lake. Flashrom works fine, and logs and
descriptor dumps look good. Also, register and descriptor output
agree on the flash layout and permissions.
Change-Id: I40db4773f127bec63e377e1d2ab402b47edf9a61
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add support for Cannon Lake U Premium (CFL-U/WHL-U).
Same as discrete 300-series CNP PCH.
Tested on a WHL-U laptop w/unlocked IFD.
Change-Id: I8a318d63cf408a3b2cec436a3fa6e26cf8552ead
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Only minor differences in the Firmware Descriptor, compared to their
predecessors.
We extend our check on the `ICCRIBA` field in the descriptor to dis-
tinguish it from older generation. Alas, the `freq_read` field was
repurposed, so we can't use it as sanity check any more.
Change-Id: I1c2d1e8916cecd756e7ac1f0ba221d7cc361ba02
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The Cannon Lake "300 Series" PCHs [1,2] share the register layout of the
Skylake "100 Series". Mark them as BAD until `ichspi.c` is adapted.
[1] Intel(R) 300 Series and Intel(R) C240 Series
Chipset Family Platform Controller Hub
Datasheet - Volume 1 of 2
Revison 4 (Dec 2018)
Document Number 337347
[2] Intel(R) 300 Series Chipset Families Platform Controller Hub
Datasheet - Volume 2 of 2
Revision 2? (Oct 2018)
Document Number 337348
Change-Id: If0b54799d5b93169ee660409bad57ae14677340c
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jeremy Soller <jackpot51@gmail.com>
It's almost identical to 100 series PCHs and later. There are some
additional FREGs (12..15). To not clutter the `if` conditions further,
make more use of `switch` statements.
Tested on Kontron mAL10. Mark it as DEP as usually the last sector
is not covered by the descriptor layout and can't be read.
Change-Id: I1c464b5b3d151e6d28d5db96495fe874a0a45718
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/30995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
It works the same as 100 series PCHs and on. The SPI device is at
0:0d.2, though. Mark as BAD until `ichspi` is revised.
Change-Id: I7b1ad402ba562b7b977be111f8cf61f1be50843a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/30994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
We used to bail out on any unknown laptop. However, modern systems with
SPI flashes don't suffer from the original problem. Even if a flash chip
is shared with the EC, the latter has to expect the host to send regular
JEDEC SPI commands any time.
So instead of bailing out, we limit the set of buses to probe. If we
suspect to be running on a laptop, we only allow probing of SPI and
opaque programmers. The user can still use the existing force options
to probe all buses.
This will obsolete some board-enables that could be moved to `print.c`
in follow-up commits.
Change-Id: I1dbda8cf0c10d7786106f14f0d18c3dcce35f0a3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/28716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Tested on a Supermicro X10SLM+-F. The flash chip has been read, written,
and erased many times without issue. Most boards with this chipset will
have the ME region locked, hence the selection of DEP.
Change-Id: I25126b94e691289a7b29dd81d5c864854a4e0245
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested reading, writing and erasing the internal flash chip using an HP
Pavilion dv6-2125ef laptop with an Intel PM55 chipset. However, since
all ME-enabled chipsets are marked as DEP instead of OK, this one shall
follow suit as well.
Change-Id: I667ea970be11a35b480e0e7c69a1fdf9afa08762
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/29437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested on an ASRock H81M-HDS. The flash chip has been read, written, and
erased many times without issue. Most boards with this chipset will have
the ME region locked, hence the selection of DEP.
Change-Id: I30aae956b2851c741e59403f5e49b80b5ba7c5e4
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested reading, writing and erasing the internal flash chip using a
Toshiba L755 laptop with an Intel HM65. However, since all ME-enabled
chipsets are marked as DEP instead of OK, this one shall follow suit as
well.
Change-Id: I3fd62c3b4ee17a403cc3937422f3d850fd2878a4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
As per Laurent Grimaud on the mailing list. I also have said chipset.
Since all ME-enable chipsets are marked as DEP instead of OK, this
one shall follow suit as well.
Change-Id: Ie195e8ec9ea1a2393e31bebdaede4fd3c3301a17
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested reading, writing and erasing the internal flash chip using an HP
630 laptop with an Intel HM55. However, since all ME-enabled chipsets
are marked as DEP instead of OK, this one shall follow suit as well.
Change-Id: Iaedd5bdc34dfff9b8588a3f4e1ad46460077fdf9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
I can confirm a successful reading and writing of MX25L8005 (SPI) on a HP t5550
Thin Client (AMI BIOS 786R9 v1.04).
Change-Id: I190253b0c1920747b710ed7155e78191cce139eb
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/23030
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Avoid attempting to read the SPI bases from the location 0x00000000, all
zeroes mean that the chipset's MMIO area is not enabled.
Change-Id: I5d3a1ba695153e854e0979ae634f8ed97e6b6293
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/23029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This patch has been tested on a board similar to AMD Bettong.
00:14.0 SMBus [0c05]: Advanced Micro Devices, Inc. [AMD] FCH SMBus
Controller [1022:790b] (rev 4a)
00:14.3 ISA bridge [0601]: Advanced Micro Devices, Inc. [AMD] FCH LPC
Bridge [1022:790e] (rev 11)
root@qt5022-fglrx:~# ./flashrom -p internal -w kk.rom
flashrom v0.9.9-unknown on Linux 4.10.0-qtec-standard (x86_64)
flashrom is free software, get the source code at
https://flashrom.org
Calibrating delay loop... OK.
coreboot table found at 0x9ffd6000.
Found chipset "AMD FP4".
Enabling flash write... OK.
Found Micron/Numonyx/ST flash chip "N25Q128..1E" (16384 kB, SPI)
mapped at physical address 0x00000000ff000000.
Reading old flash chip contents... done.
Erasing and writing flash chip... Erase/write done.
Verifying flash... VERIFIED.
Change-Id: I66a240ebc8382cc7e5156686045aee1a9d03fe6d
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-on: https://review.coreboot.org/21429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This adds PCI IDs for C620-series PCHs and adds
CHIPSET_C620_SERIES_LEWISBURG as a new entry in the ich_chipset enum.
Lewisburg is very similar to Sunrise Point for Flashrom's purposes,
however one important difference is the way the "number of masters" is
interpreted from the flash descriptor (0-based vs. 1-based). There are
also new flash regions defined.
Change-Id: I96c89bc28bdfcd953229c17679f2c28f8b874d0b
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/20922
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
